MARC Record from harvard_bibliographic_metadata

LEADER: 04381nam a22004815a 4500
001 014277499-5
005 20150113020620.0
008 100301s2005 xxu| s ||0| 0|eng d
020 $a9780387274461
020 $a9780387274461
020 $a9780387210179
024 7 $a10.1007/b139084$2doi
035 $a(Springer)9780387274461
040 $aSpringer
050 4 $aTK7895.M5
072 7 $aUYF$2bicssc
072 7 $aCOM011000$2bisacsh
082 04 $a004.1$223
100 1 $aDandamudi, Sivarama P.$eauthor.
245 10 $aGuide to RISC Processors :$bfor Programmers and Engineers /$cby Sivarama P. Dandamudi.
264 1 $aNew York, NY :$bSpringer New York,$c2005.
300 $aXV, 387 p.$bonline resource.
336 $atext$btxt$2rdacontent
337 $acomputer$bc$2rdamedia
338 $aonline resource$bcr$2rdacarrier
347 $atext file$bPDF$2rda
505 0 $aOverview -- Processor Design Issues -- RISC Principles -- Architectures -- MIPS Architecture -- SPARC Architecture -- PowerPC Architecture -- Itanium Architecture -- ARM Architecture -- MIPS Assembly Language -- SPIM Simulator and Debugger -- Assembly Language Overview -- Procedures and the Stack -- Addressing Modes -- Arithmetic Instructions -- Conditional Execution -- Logical and Shift Operations -- Recursion -- Floating-Point Operations.
520 $aRecently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel’s 64-bit processor Itanium. This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM, and Itanium. Initial chapters explain the differences between the CISC and RISC designs and clearly discuss the core RISC design principles. The text then integrates instruction on MIPS assembly language programming, thereby enabling readers to concretely grasp concepts and principles introduced earlier. Readers need only have a basic knowledge of any structured, high-level language to obtain the full benefits here.
520 $aFeatures: *Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience *Presents material in a manner suitable for flexible self-study • Assembly language programs permit reader executables using the SPIM simulator • Integrates core concepts to processor designs and their implementations • Supplies extensive and complete programming examples and figures • Contains chapter-by-chapter overviews and summaries * Provides source code for the MIPS language at the book’s website Guide to RISC Processors provides a uniquely comprehensive introduction and guide to RISC-related concepts, principles, design philosophy, and actual programming, as well as the all the popular modern RISC processors and their assembly language. Professionals, programmers, and students seeking an authoritative and practical overview of RISC processors and assembly language programming will find the guide an essential resource. Sivarama P.
520 $aDandamudi is a professor of computer science at Carleton University in Ottawa, Ontario, Canada, as well as associate editor responsible for computer architecture at the International Journal of Computers and Their Applications. He has more than two decades of experience teaching about computer systems and organization. Key Topics * Processor design issues * Evolution of CISC and RISC processors * MIPS, SPARC, PowerPC, Itanium, and ARM architectures * MIPS assembly language * SPIM simulator and debugger * Conditional execution * Floating-point and logical and shift operations * Number systems Computer Architecture/Programming Beginning/Intermediate Level
650 0 $aComputer science.
650 0 $aMicroprogramming.
650 0 $aComputer network architectures.
650 0 $aSoftware engineering.
650 14 $aComputer Science.
650 24 $aProcessor Architectures.
650 24 $aControl Structures and Microprogramming.
650 24 $aSoftware Engineering/Programming and Operating Systems.
650 24 $aComputer Systems Organization and Communication Networks.
650 24 $aProgramming Techniques.
776 08 $iPrinted edition:$z9780387210179
988 $a20150113
906 $0VEN