| Record ID | ia:digitalvlsisyste0000rama |
| Source | Internet Archive |
| Download MARC XML | https://archive.org/download/digitalvlsisyste0000rama/digitalvlsisyste0000rama_marc.xml |
| Download MARC binary | https://www.archive.org/download/digitalvlsisyste0000rama/digitalvlsisyste0000rama_meta.mrc |
LEADER: 01002nam a22003011a 4500
001 013715901
003 Uk
005 20180217195000.0
008 070416s2007 ne 000 0 eng d
015 $aGBA728806$2bnb
016 7 $a013715901$2Uk
020 $a9781402058288 (hbk.) :$c£77.00
020 $a1402058284 (hbk.) :$c£77.00
040 $aStDuBDS$beng$cStDuBDS$dUk
042 $aukblsr
082 04 $a621.395$222
100 1 $aRamachandran, S.$q(Seetharaman)
245 10 $aDigital VLSI systems design :$ba design manual for implementation of projects on FPGAs and ASICs using Verilog /$cSeetharaman Ramachandran.
260 $aDordrecht ;$aLondon :$bSpringer,$c2007.
300 $a1 v.
336 $atext$2rdacontent
337 $aunmediated$2rdamedia
338 $avolume$2rdacarrier
500 $aFormerly CIP.$5Uk
650 0 $aIntegrated circuits$xVery large scale integration.
650 0 $aDigital electronics.
650 0 $aIntegrated circuits$xDesign and construction.
916 $a100=NEW