| Record ID | ia:logicsynthesisfo0000unse |
| Source | Internet Archive |
| Download MARC XML | https://archive.org/download/logicsynthesisfo0000unse/logicsynthesisfo0000unse_marc.xml |
| Download MARC binary | https://www.archive.org/download/logicsynthesisfo0000unse/logicsynthesisfo0000unse_meta.mrc |
LEADER: 01033cam 2200277Ia 4500
001 ocm49351393
005 20020619170126.0
008 020312s2002 gw a b 001 0 eng
010 $a2002021125
020 $a3540431527 (alk. paper)
040 $aDLC$cDLC$dC#P$dMIA
049 $aMIAS
050 00 $aTK7868.L6$bL5864 2002
245 00 $aLogic synthesis for asynchronous controllers and interfaces /$cJ. Cortadella ... [et al.]
260 $aBerlin ;$aNew York :$bSpringer,$cc2002
300 $axiii, 273 p. :$bill. ;$c24 cm
440 0 $aSpringer series in advanced microelectronics,$x1437-0387 ;$v8
504 $aIncludes bibliographical references (p. [257]-269) and index
650 0 $aLogic circuits
650 0 $aElectronic controllers
650 0 $aAsynchronous circuits
700 1 $aCortadella, J.$q(Jordi),$d1962-
907 $a.b29407928$b11-15-04$c06-05-02
998 $ascl$b06-19-02$cm$da$e-$feng$ggw $h0$i1
947 $akis
945 $g1$i35054025653086$j0$lscli $o $p$0.00$q $r $s-$t0$u1$v0$w0$x0$y.i3883036x$z06-19-02