MARC record from Internet Archive

LEADER: 10077pam 22003254a 4500
001 9919742850001661
005 20150423122517.0
008 030409s2003 nyua b 001 0 eng
010 $a 2003051161
020 $a0071409866 (alk. paper)
035 $a(CSdNU)u176516-01national_inst
035 $a(OCoLC)52133200
035 $a(OCoLC)52133200
040 $aDLC$cDLC$dYDX$dOrPss
042 $apcc
049 $aCNUM
050 00 $aTK5105.543$b.L47 2003
082 00 $a004.6$221
100 1 $aLekkas, Panos C.
245 10 $aNetwork processors :$barchitectures, protocols, and platforms / $cPanos C. Lekkas.
260 $aNew York :$bMcGraw-Hill,$cc2003.
300 $axxiii, 456 p. :$bill. ;$c25 cm.
504 $aIncludes bibliographical references and index.
505 0 $aFundamentals -- The Evolution of Network Technology: Distributed Computing and the Convergence of Networks -- In the Beginning -- Departmental Machines Erode the Mainframe's Following -- The First Local Area Network (LAN) -- Moving Mainframes onto Desks: PC and Workstations -- The Client-Server Model -- Packet-Switched Versus Circuit-Switched Networks -- The Internet, Routing, and Associated Web Technologies -- Network Management -- Switched LANs, Fast Ethernet, and Fiber-Distributed Data Interface (FDDI) -- IP Networks: Intranets and Extranets -- IP Telephony -- ATM, LAN Emulation (LANE), Multiprotocol over Asynchronous Transfer Mode (MPOA), and IP over ATM -- Wireless Networks and Mobility -- 1 Gigabit and 10 Gigabit Ethernet -- Storage Networks -- The Convergence of Networks -- Optical Networking Breakthroughs -- Processors: RISC, Digital Signal Processor (DSP), and Integration Toward System-on-a-Chip (SOC) -- The Quest for Bandwidth and QoS -- Switching Evolution: From Layer 2 Switches to Routers to Layer 3 Switches -- MPLS, Lambda Switching, and Wavelength Routers -- VPNs -- Security Co-processors -- Traffic Engineering (TE) -- QoS -- Performance Constraints Imposed on Communications Network Equipment -- Network Processors: Justification -- What Are Network Processors? -- Functional Blocks in Networking Equipment -- The PHY Interface -- Switch Fabric -- Packet Processing -- Host Processing -- A Closer Look at Packet Processing -- Trade-offs When Designing with Standard Off-the-Shelf CPUs -- Trade-offs When Designing with ASICs -- The Network Processors' Breakthrough -- The Value Proposition of Network Processors -- Network Processors: Categories -- Packet Processing -- Network Contexts: Client, Access, Edge, and Core -- The Timing of the Network-Processing Evolution -- The Overriding Requirements for Network Equipment -- Data and Control Plane Processing -- Packet-Processing Operations -- Packet framing -- Pattern search and packet classification -- CAM (Content-Addressable Memory) -- Search Engines -- Packet Parsing -- Packet Classification and Fast Forwarding -- Modification -- Switching -- Traffic Management and Other Operations -- Network Processor Architectures -- IBM PowerNP(tm) -- IBM PowerNP: The Big Picture -- Architecture -- Major Functional Blocks in the NP4GS3 -- Special Coprocessor and Assist Hardware -- Software Architecture -- Software and Systems Development Around the NP4GS3 -- Performance -- The NP4GX: IBM's Second-Generation OC-48 Network Processor -- Trade-offs when Designing with NP4GS3 -- Intel IXA Network Processors -- Intel IXA: The Big Picture -- Architecture -- Software Architecture -- Software and Systems Development Around IXA Architecture NPUs -- Systems Considerations and Trade-offs When Designing with Intel NPUs -- AMCC nP(tm) Family of Network Processors -- nP(tm) Architecture: The Big Picture -- Developing Software for the nP Family of Network Processors -- Traffic Management -- Switch Fabric -- Systems Considerations When Designing withAMCC nP Family NPUs -- Fifth-generation Technology -- Agere PayloadPlus(r) Family of Network Processors -- PayloadPlus(r) Architecture: The Big Picture -- FPP -- RSP -- ASI -- The DLB Algorithm -- Agere's APP750NP (ex-NP10) and APP750TM (ex-TM10) Chipset -- The APP550 (ex-INP5) Network Processor -- Developing Systems and Software for the PayloadPlus Family of NPUs -- Motorola's C-Port(tm) Family of Network Processors -- C-Port: The Big Picture -- NPU Architecture -- The Q-5 TMC -- Developing Software for the C-Port Family of Network Processors -- Systems Considerations When Designing with C-Port NPUS -- Other NPU Architectures -- Silicon Access Networks' iFlow(tm) Chipset -- Bay Microsystems' Montego(tm) and the InP(tm) Family -- Cognigine -- EZchip TOPcore(tm) -- Vitesse IQ(tm) Family of Network Processors -- Wintegra -- Xelerated Packet Devices -- Other Approaches -- Alternative Approaches to Network Processing: Net ASICs and Designing with IP Cores -- Net ASICs -- Designing with IP Cores -- MIPS Technologies -- ClearSpeed Technology -- Tensilica -- FLIX: Configurable VLIW -- ARC Cores -- Improv Systems -- Peripheral Chips Supporting Network Processors: Storage Processors, Classification Processors, Search Engines, Switch Fabrics, and Traffic Managers -- Storage Network Processors (SNPs) -- Storage Network Processing: The Context -- SAN-Enabling Technologies -- Fibre Channel -- IP Storage -- Network Interface Card (NIC) -- Storage HBAs -- iSCSI Adapters -- Storage Virtualization -- iSCSI -- FCIP -- Fibre-Channel-to-iSCSI Bridging -- Typical Applications for an SNP -- Requirements for an SNP -- TCP Termination Engines or TCP-Offload Engines (TOEs) -- Trebia Networks' SAN Protocol Processor (SPP) -- Silverback Systems iSNAP(tm) Architecture -- Security Issues in Storage Network Processing -- Secure SNP Trends and Concerns Moving Forward -- Search Engines -- The Packet Classification Context of a Search Engine -- Content-Addressable Memory (CAM) -- Pros and Cons -- CAM Structure -- Management of Tables Inside a CAM -- Systems Engineering Issues Surrounding the Use of CAMs -- Reproaches Against CAM-Based Search Engines -- Going Forward -- Alternative Ways of Implementing a Search Engine -- Classification Processors -- Two Types of Packet Classification -- Lookup and Forwarding -- Algorithms for Managing Lookup Table Updates -- Algorithms and Data Structures to Support Lookup and Forwarding -- Deep Packet Classification -- Classification Based on Multiple Fields -- Implementation -- Classification Processors or CAMs? -- Integrated Classification or Standalone? -- Case Study: Raqia's Regular Expression Classification Coprocessor -- Switch Fabrics -- The Definition of Switch Fabric -- The Basics of Switching -- Blocking -- Basic Switching Elements -- Generic Types of Switching Platforms -- The Evolution of the Multiservice Router/Switch -- Backplane Description -- The Scalability of Switch Fabrics -- The Redundancy of Switch Fabrics -- Routing/Switching Systems Considerations -- Switch Fabric Architectures -- Input-Buffered and Output-Buffered Switches -- Buffered Crossbar -- Arbitrated Crossbar -- Shared Memory Switches -- Multistage switches -- Banyan-Based Switches -- Batcher-Banyan Switches -- A Couple of Commercial Examples -- IBM PowerPRS(tm) Switch Fabrics -- Agere Switch Fabrics -- Traffic Managers -- The Definition and Purpose of a Traffic Manager -- Traffic Managers as Standalone Chips -- Fundamental Concepts in Traffic Management -- QoS-Oriented Protocols -- RSVP -- IntServ -- DiffServ -- Major Tasks and Algorithms -- Statistics -- Traffic Marking, Shaping, and Policing -- Congestion Management -- Scheduling and Buffer Management -- Traffic Manager Case Studies -- Putting Everything Together -- Systems Engineering Issues -- Memory Subsystems -- DRAM Flavors -- SRAM Flavors -- CAM -- NPU Architecture Issues -- Software Development Issues -- Software Development Cost -- A Real-Life Case Study: Design Issues with an MSR -- Task Definition -- Design Approach -- Preliminary Design Outlook -- Switch Fabric -- System Considerations -- Resources Budget -- Security Coprocessors -- Security Coprocessors -- Secure Communications Applications in Network Processing -- VPNs -- Conducting Secure Electronic Transactions -- Wireless Security -- Cryptography: Some Basic Notions -- Private- or Symmetric-Key Encryption -- Public-Key Cryptography -- Block Ciphers, Stream Ciphers, and Cryptographic Modes -- Block Ciphers -- Stream Ciphers -- Cryptographic Modes -- Important Cryptographic Considerations in Communications -- Weak Keys -- Protocol-Sensitive Encryption -- Hashing -- Message Authentication Codes (MACs) -- Digital Signatures -- Session Key Exchange -- Digital Certificates -- Embedded Sequence Counters -- Address Tunneling -- Timestamp (Nonrepudiation) -- Rekeying -- Security Associations (SAs) -- Common Cryptographic Algorithms -- Diffie-Hellman (DH) -- Common Public-Key Cryptography Algorithms -- Standardized Security Protocols -- IPsec -- SSL -- Security Coprocessors: A Classification -- Systems Considerations when Engaging a Security Coprocessor -- Overview of Network-Processor Products and Platforms -- Typical Traffic Load (in Millions of Packets per Second) Correspondence at Various Link Speeds and Packet Sizes -- Standardization Efforts in Network Processing -- Network Processing Forum (NPF) -- Hardware Working Group (HWG) -- Software Working Group (SWG) -- Benchmarking Working Group (BWG) -- Technical Education and Marketing Working Group (TEMWG) -- Implementation Agreements (IAs) -- Optical Internetworking forum (oip) -- ATM Forum -- Institute of Electrical and Electronics Engineers (IEEE) -- 10 Gigabit Ethernet Alliance -- Metro Ethernet Forum (MEF) -- Internet Engineering Task Force (IETF) -- InfiniBand -- RapidIO -- HyperTransport -- Performance Benchmarking -- Industry Forums -- Industry Analysts.
650 0 $aRouters (Computer networks)$xEquipment and supplies.
650 0 $aMicroprocessors.
650 0 $aApplication-specific integrated circuits
949 $aTK 5105.543 .L47 2003$i31786101565114
994 $a92$bCNU
999 $aTK 5105.543 .L47 2003$wLC$c1$i31786101565114$d4/15/2004$f4/15/2004$g1 $lCIRCSTACKS$mNULS$rY$sY$tBOOK$u11/3/2003