MARC record from Internet Archive

LEADER: 04269cam 2200493 a 4500
001 ocm27429428
003 OCoLC
005 20170821145309.0
008 930125s1993 maua b 101 0 eng
010 $a 93012230
040 $aDLC$beng$cDLC$dUKM$dOCL$dBAKER$dBTCTA$dYDXCP$dZAP$dGBVCP$dOCLCO$dOCLCF$dOCLCQ$dOCLCO$dOCL$dOCLCO
015 $aGB9349549$2bnb
016 7 $a026-20235$2uk
019 $a810494146
020 $a0262023571
020 $a9780262023573
035 $a(OCoLC)27429428$z(OCoLC)810494146
050 00 $aTK7874$b.R47 1993
082 00 $a621.39/5$220
245 00 $aResearch on integrated systems :$bproceedings of the 1993 symposium /$cedited by Gaetano Borriello and Carl Ebeling.
260 $aCambridge, Mass. :$bMIT Press,$c℗♭1993.
300 $aviii, 337 pages :$billustrations ;$c24 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
338 $avolume$bnc$2rdacarrier
504 $aIncludes bibliographical references and index.
505 0 $aThe Design of the Caltech Mosaic C Multicomputer / Charles L. Seitz, Nanette J. Boden and Jakov Seizovic, and Wen-King Su -- RAID-II: Design and Implementation of a Large Scale Disk Array Controller / R. Katz, P. Chen, A. Drapeau, E. Lee, K. Lutz, E. Miller, S. Seshan and D. Patterson -- Formal Specification of Abstract Memory Models / David L. Dill, Seungjoon Park and Andreas G. Nowatzyk -- An Area-Universal VLSI Circuit / Paul Bay and Gianfranco Bilardi -- Delay Fault Testing: Trading Fault Coverage, Test Set Size, and Performance / William K. Lam, Alexander Saldanha, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli -- Programmable Active Memories: A Performance Assessment / Patrice Bertin, Didier Roncin and Jean Vuillemin -- A High-Speed FPGA Using Programmable Mini-Tiles / Paul Chow, Soon Ong Seo, Kevin Chung, Gerard Paez and Jonathan Rose -- Spectral K-Way Ratio-Cut Partitioning and Clustering / Pak K. Chan, Martine Schlag and Jason Y. Zien.
505 0 $aHigh Speed 64-b CMOS Datapath / John Wawrzynek and Bertrand Irissou -- A 32kb GaAs SRAM with Electronically Programmable Redundancy / Ajay Chandna and Richard B. Brown -- A Scalable Systolic Multiprocessor System for Analysis of Biological Sequences / Raj K. Singh, Stephen G. Tell, C. Thomas White, Doug Hoffman, Vernon L. Chi and Bruce W. Erickson -- A Field-Programmable Gate Array for Systolic Computing / Frederick Furtek -- Edge-Triggering vs. Two-Phase Level-Clocking / Marios C. Papaefthymiou and Keith H. Randall -- Designing Salphasic Clock Distribution Systems / Vernon L. Chi -- Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS / Saed G. Younis and Thomas F. Knight, Jr. -- Multi Module Focal Plane Processing Sensor with Parallel Analog Support for Computer Vision / Marc Tremblay, Denis Laurendeau and Denis Poussart -- Low-Power DSP Circuit Design Using Bit-Level Pipelined Maximally-Parallel Architectures / Phillip J. Duncan, Shobana Swamy and Rajeev Jain.
505 0 $aImplementation of a Packet Switching Device as a Delay-Insensitive Circuit / Jelio Yantchev and Ivailo Nedelchev -- Electrical Design of a 1GByte/Sec High Performance Backplane Using Low Voltage Swing CMOS (GTL) / Christopher Cheng and Leo Yuan -- High-Performance Bidirectional Signalling in VLSI Systems / Larry R. Dennison, Whay S. Lee and William J. Dally -- A Family of Routing and Communication Chips Based on the Mosaic / Charles L. Seitz and Wen-King Su.
650 0 $aIntegrated circuits$xVery large scale integration$vCongresses.
650 7 $aIntegrated circuits$xVery large scale integration.$2fast$0(OCoLC)fst00975602
653 0 $aIntegrated$aVery$aCongresses
655 7 $aConference papers and proceedings.$2fast$0(OCoLC)fst01423772
700 1 $aBorriello, Gaetano.
700 1 $aEbeling, Carl.
856 41 $3Table of contents$uhttp://www.gbv.de/dms/bowker/toc/9780262023573.pdf
938 $aBaker & Taylor$bBKTY$c65.00$d65.00$i0262023571$n0002272921$sactive
938 $aBaker and Taylor$bBTCP$n93012230
938 $aYBP Library Services$bYANK$n146391
029 1 $aAU@$b000009854809
029 1 $aGBVCP$b122774647
029 1 $aNLGGC$b102550107
994 $aZ0$bPMR
948 $hNO HOLDINGS IN PMR - 112 OTHER HOLDINGS