| Record ID | marc_columbia/Columbia-extract-20221130-003.mrc:168079475:1267 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-003.mrc:168079475:1267?format=raw |
LEADER: 01267fam a2200337 a 4500
001 1153626
005 20220601220608.0
008 920221t19921992maua b 001 0 eng
010 $a 92008800
020 $a0890065802
035 $a(OCoLC)25508138
035 $a(OCoLC)ocm25508138
035 $9AGL3763CU
035 $a(NNC)1153626
035 $a1153626
040 $aDLC$cDLC$dDLC
050 00 $aTK7888.4$b.R35 1992
082 00 $a621.39/5/0287$220
100 1 $aRajsuman, Rochit.$0http://id.loc.gov/authorities/names/n89658334
245 10 $aDigital hardware testing :$btransistor-level fault modeling and testing /$cRochit Rajsuman.
260 $aBoston :$bArtech House,$c[1992], ©1992.
300 $axv, 317 pages :$billustrations ;$c24 cm
336 $atext$2rdacontent
337 $aunmediated$2rdamedia
338 $avolume$2rdacarrier
500 $a"Annotated bibliography": p. 303-310.
504 $aIncludes bibliographical references and index.
650 0 $aElectronic digital computers$xCircuits$xTesting$xData processing.
650 0 $aIntegrated circuits$xVery large scale integration$xTesting$xData processing.
650 0 $aFault-tolerant computing.$0http://id.loc.gov/authorities/subjects/sh85047488
852 00 $boff,eng$hTK7888.4$i.R35 1992