| Record ID | marc_columbia/Columbia-extract-20221130-004.mrc:217719342:1728 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-004.mrc:217719342:1728?format=raw |
LEADER: 01728fam a2200313 a 4500
001 1671323
005 20220608210558.0
008 941007t19951995maua b 001 0 eng
010 $a 94041225
020 $a0867202041
035 $a(OCoLC)31374251
035 $a(OCoLC)ocm31374251
035 $9AKT6970CU
035 $a(NNC)1671323
035 $a1671323
040 $aDLC$cDLC$dDLC$dOrLoB
050 00 $aQA76.9.A73$bF58 1995
082 00 $a004.2/2$220
100 1 $aFlynn, Michael J.,$d1952-$0http://id.loc.gov/authorities/names/n85067711
245 10 $aComputer architecture :$bpipelined and parallel processor design /$cMichael J. Flynn.
260 $aBoston, MA :$bJones and Bartlett,$c[1995], ©1995.
300 $axix, 788 pages :$billustrations ;$c26 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
504 $aIncludes bibliographical references and index.
505 00 $g1.$tArchitecture and Machines --$g2.$tTime, Area, and Instruction Sets --$g3.$tData: How Programs Behave --$g4.$tPipelined Processor Design --$g5.$tCache Memory --$g6.$tMemory System Design --$g7.$tConcurrent Processors --$g8.$tShared Memory Multiprocessors --$g9.$tI/O and the Storage Hierarchy --$g10.$tProcessor Studies --$tAppendix A DTMR Cache Miss Rates --$tAppendix B SPECmark vs. DTMR Cache Performance --$tAppendix C Modeling System Effects in Caches --$tAppendix D New DRAM Technologies --$tAppendix E M/G/1 Queues --$tAppendix F Some Details on Bus-Based Protocols.
650 0 $aComputer architecture.$0http://id.loc.gov/authorities/subjects/sh85029479
650 0 $aMicroprocessors$xDesign and construction.$0http://id.loc.gov/authorities/subjects/sh2010101683
852 00 $boff,eng$hQA76.9.A73$iF58 1995