| Record ID | marc_columbia/Columbia-extract-20221130-004.mrc:574605659:1775 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-004.mrc:574605659:1775?format=raw |
LEADER: 01775mam a2200301 a 4500
001 1953394
005 20220609034459.0
008 970116t19971997maua b 001 0 eng
010 $a 97105422
020 $a0792398270 (acid-free paper)
035 $a(OCoLC)ocm36430770
035 $9AMF3411CU
035 $a1953394
040 $aDLC$cDLC$dOrLoB-B
050 00 $aTK7874.75$b.B45 1997
245 00 $aBehavioral synthesis and component reuse with VHDL /$cAhmed A. Jerraya [and others] ; contribution by E. Berrebi, W. Cesario, P. Guillaume.
260 $aBoston :$bKluwer Academic Publishers,$c[1997], ©1997.
300 $axix, 263 pages :$billustrations ;$c24 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
504 $aIncludes bibliographical references (p. 247-255) and index.
505 00 $g1.$tIntroduction --$g2.$tModels for Behavioral Synthesis --$g3.$tVHDL Modeling for Behavioral Synthesis --$g4.$tBehavioral VHDL Description Styles for Design Reuse --$g5.$tAnatomy of a Behavioral Synthesis System Based on VHDL --$g6.$tCase Study: Hierarchical Design Using Behavioral Synthesis --$g7.$tCase Study: Modular Design Using Behavioral Synthesis.
650 0 $aIntegrated circuits$xVery large scale integration$xDesign and construction$xData processing.$0http://id.loc.gov/authorities/subjects/sh2009127318
650 0 $aVHDL (Computer hardware description language)$0http://id.loc.gov/authorities/subjects/sh89002702
650 0 $aComputer-aided design.$0http://id.loc.gov/authorities/subjects/sh85029476
650 0 $aSystem design$xData processing.$0http://id.loc.gov/authorities/subjects/sh85131737
700 1 $aJerraya, Ahmed A.$q(Ahmed Amine)$0http://id.loc.gov/authorities/names/n97007979
852 00 $boff,eng$hTK7874.75$i.B45 1997