MARC Record from marc_columbia

LEADER: 03176mam a2200373 a 4500
001 2132723
005 20220615212235.0
008 970925t19981998maua b 001 0 eng
010 $a 97042097
015 $aGB98-6115
020 $a0792380762 (acid-free paper)
035 $a(OCoLC)ocm37725641
035 $9ANH4769CU
035 $a2132723
040 $aDLC$cDLC$dUKM$dOrLoB-B
050 00 $aTK7874.66$b.I43 1998
082 00 $a621.39/5$221
100 1 $aIman, Sasan.$0http://id.loc.gov/authorities/names/n97097743
245 10 $aLogic synthesis for low power VLSI designs /$cby Sasan Iman and Massoud Pedram.
260 $aBoston :$bKluwer Academic Publishers,$c[1998], ©1998.
300 $axiv, 236 pages :$billustrations ;$c24 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
504 $aIncludes bibliographical references and index.
505 00 $gI.$tBackground, Terminology, and Power Modeling.$g1.$tIntroduction.$g2.$tTechnology Independent Power Analysis and Modeling --$gII.$tTwo-level Function Optimization for Low Power.$g3.$tTwo-Level Logic Minimization in CMOS Circuits.$g4.$tTwo-Level Logic Minimization in PLAs --$gIII.$tMulti-level Network Optimization for Low Power.$g5.$tLogic Restructuring for Low Power.$g6.$tLogic Minimization for Low Power.$g7.$tTechnology Dependent Optimization for Low Power /$rChi-ying Tsui.$g8.$tPost Mapping Structural Optimization for Low Power --$gIV.$tPower Optimization Methodology.$g9.$tPOSE: Power Optimization and Synthesis Environment --$gV.$tConclusion.$g10.$tConcluding Remarks.
520 $aLogic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level.
520 8 $aLogic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-independent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power.
520 8 $aIt also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs in written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
650 0 $aLow voltage integrated circuits$xDesign and construction$xData processing.
650 0 $aLogic design$xData processing.$0http://id.loc.gov/authorities/subjects/sh85078119
650 0 $aComputer-aided design.$0http://id.loc.gov/authorities/subjects/sh85029476
650 0 $aMetal oxide semiconductors, Complementary$xDesign and construction$xData processing.
700 1 $aPedram, Massoud.$0http://id.loc.gov/authorities/names/n95074872
852 00 $boff,eng$hTK7874.66$i.I43 1998