MARC Record from marc_columbia

LEADER: 07314mam a2200361 a 4500
001 2232275
005 20220615235230.0
008 981210t19981998njua b 101 0 eng d
010 $a 98085598
020 $a0780349652 (softbound edition)
020 $a0780349660 (microfiche edition)
035 $a(OCoLC)ocm40468263
035 $9ANW3106CU
035 $a(NNC)2232275
035 $a2232275
040 $aLHL$cLHL$dOrLoB-B
090 $aTK7870.15$b.E42 1998
111 2 $aTopical Meeting on Electrical Performance of Electronic Packaging$n(7th :$d1998 :$cWest Point, N.Y.)
245 10 $aElectrical performance of electronic packaging :$bOctober 26-28, 1998, The Hotel Thayer, West Point, New York /$csponsored by the IEEE Microwave Theory and Techniques Society and the IEEE Components, Packaging and Manufacturing Technology Society.
260 $aPiscataway, New Jersey :$bIEEE Service Center,$c[1998], ©1998.
300 $axii, 300 pages :$billustrations ;$c28 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
500 $a"7th Topical Meeting on Electrical Performance of Electronic Packaging ..."--P. iii.
500 $a"IEEE Catalog Number: 98TH8370"--verso of T.p.
504 $aIncludes bibliographic references author and index.
505 00 $tReaching the Limits of CMOS Technology -- $tElectrical Performance of Chip-On-Chip Modules -- $tModeling, Simulation, and Design Methodology of The Interconnect Packaging of an Ultra-High Speed Source Synchronous Bus -- $tFirst Level Package Design Considerations for the IBM's S/390 G5 Server -- $tBus Pumping at GBIT/S Data Rate on MCM -- $tDetermination of the Optimal Signal/Ground Configuration of A Multi-Pins Connector for Minimal Crosstalk -- $tDesign Methodology for On-Chip Interconnects -- $tSignal Propagation on Seamless High Off-Chip Connectivity (SHOCC) Interconnects -- $tFrequency-dependent Crosstalk Modeling for On-chip Interconnections -- $tFlip-Chip Power Distribution -- $tNational Institute of Standards and Technology Programs in Electrical Measurements for Electronic Interconnections -- $tInductance Measurement of Lead-Frame Packages -- $tHigh Frequency Limitations of the JEDEC 123 Guideline -- $tElectrical Characterization of Ball Grid Array Packages from S-parameter Measurements below 500MHz -- $tOn-chip Capacitor Measurement for High Performance Microprocessor -- $tCharacterization of Frequency Dependent Dielectric Packaging Media Using Differential and Multiple-Reflection Techniques on a Precision Stripline Test Structure -- $tPLL Phase Error and Power Supply Noise -- $tA Novel High Isolation Interconnect for Broadband Mixed Signal Silicon MMICs -- $tInvestigations of Multi-Layer Ceramic-Based MCM Technology -- $tModeling of Free Space Holographic Optical Link for Board Level Interconnect -- $tTemperature Stable Thermoplastic Microwave Materials and Copper Laminates -- $tConsiderations of Characterizing Standard SMT Packages for RFIC Applications -- $tA Novel Electrical Performance Analysis for Leaded Packages -- $tSimulation and Evaluation of Ground Bounce Induced Crosstalk in a Mixed Logic Ball Grid Array Substrate Design -- $tA Custom Package Autoprober -- $tGaAs Multichip Packaging using the Selectively Oxidized Porous Silicon (SOPS) Substrate -- $tModeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card -- $tTransient and Crosstalk Analysis of Interconnection Lines for Single Level Integrated Packaging Modules -- $tScaling Analysis of Interconnectivity and Crosstalk in VLSI Circuits -- $tSkin Effects Models for Transmission Line Structures using Generic SPICE Circuit Simulators -- $tEvaluation and Optimization of MCM-BGA Packages -- $tFull-Wave Electromagnetic Modeling of Interconnects with Meshed Ground Planes -- $tFast Method for the Prediction of the Capacitance of Via Through-holes -- $tElectromagnetic Interference Through Slots in Packaging Structures -- $tMulti Drop Net Topologies for MCM Off Chip Interconnection Lines -- $tHigh Frequency Equivalent Circuit Model of Via -- $tModeling of Power Distribution Systems in PCs -- $tAccurate Power Supply and Ground Plane Pair Models -- $tExtraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations -- $tIncorporating Vertical Discontinuities in Power-Bus Modeling using a Mixed-Potential Integral Equation and Circuit Extraction Formulation -- $tEffects of Power/Ground Via Distribution on the Power/Ground Performance of C4/BGA Packages -- $tReducing Simultaneous Switching Noise and EMI on Ground/Power Planes by Dissipative Edge Termination -- $tContribution of Resonance to Ground Bounce in Lossy Thin Film Plates -- $tCharacterization of Flip-Chip CMOS ASIC Simultanous Switching Noise on Multilayer Organic and Ceramic BGA/CGA Packages -- $tNorton Equivalent Modeling of Microprocessor Core Noise from Measurements -- $tRejection of SSN Coupling in Multilayer PCB Using a Conductive Layer -- $tModeling and Simulation of Thin Film Decoupling Capacitors -- $tPower Decoupling with Integral Capacitors and Area Array Connections -- $tESR and ESL of Ceramic Capacitor Applied to Decoupling Applications -- $tAnalytic Modeling of Monolithic Inductors on Semiconductor Substrates -- $tSimple Formulas to Calculate the Line Parameters of Interconnects on Conducting Substrates -- $tCAD-Oriented Equivalent Circuit Modeling of On-Chip Interconnects in CMOS Technology -- $tMicrowave & Millimeter Wave Ball Grid Array (BGA) Packages -- $tElectrical Modeling of a BGA Package for Microwave Applications - A Layer by Layer Approach -- $tFull Wave Analysis and Development of Circuit Models for Flip Chip Interconnects -- $tMicromachined Silicon Conformal Packaging for Millimeter Wave System Applications -- $tA Monolithic Spiral Transmission-Line Balun -- $tNovel Microstrip-To-Stripline Transitions For Leakage Suppression in Multilayer Microwave Circuits -- $tThe Application of the TLM Method to the Simulation of High-Speed and High-Complexity Electronic Systems -- $tNumerical Modeling of Packaging Effects Using the Finite-Difference Time-Domain Technique -- $tCanonical Package Problem Solved Using Six Different Codes -- $tImproved Integral Formulations for Fast 3-D Method-of-Moments Solvers -- $tEfficient Computation of Interconnect Capacitances Using the Domain Decomposition Approach -- $tRecent Improvements for Fast Inductance Extraction and Simulation -- $tModel Reduction for PEEC Models Including Retardation -- $tPassive Model Order Reduction of Multiconductor Interconnects -- $tEfficient Simulation of High-Speed Distributed Interconnects Using Krylov-Subspace Techniques.
650 0 $aElectronic packaging$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2008102949
650 0 $aMaterials$xElectric properties$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2010100965
710 2 $aIEEE Microwave Theory and Techniques Society.$0http://id.loc.gov/authorities/names/n82038787
710 2 $aComponents, Packaging & Manufacturing Technology Society.$0http://id.loc.gov/authorities/names/nr94012200
711 2 $aTopical Meeting on Electrical Performance of Electronic Packaging$n(7th :$d1998 :$cWest Point, N.Y.)
852 00 $boff,eng$hTK7870.15$i.E38 1998g