| Record ID | marc_columbia/Columbia-extract-20221130-005.mrc:315886738:1965 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-005.mrc:315886738:1965?format=raw |
LEADER: 01965fam a2200337 a 4500
001 2247805
005 20220616001724.0
008 950522t19961996njuaf b 001 0 eng
010 $a 95022672
020 $a0131786091
035 $a(OCoLC)32625793
035 $a(OCoLC)ocm32625793
035 $9ANY2850CU
035 $a(NNC)2247805
035 $a2247805
040 $aDLC$cDLC$dDLC$dOrLoB-B
050 00 $aTK7874.65$b.R33 1996
082 00 $a621.39/5$220
100 1 $aRabaey, Jan M.$0http://id.loc.gov/authorities/names/n95050979
245 10 $aDigital integrated circuits :$ba design perspective /$cJan M. Rabaey.
260 $aUpper Saddle River, N.J. :$bPrentice Hall,$c[1996], ©1996.
300 $axviii, 702 pages, 8 unnumbered pages of plates :$billustrations (some color) ;$c25 cm.
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
490 1 $aPrentice Hall electronics and VLSI series
504 $aIncludes bibliographical references and index.
505 00 $gCh. 1.$tIntroduction --$gCh. 2.$tThe Devices --$tAppendix A: Layout Design Rules --$tAppendix B: Small-Signal Models --$gCh. 3.$tThe Inverter --$gCh. 4.$tDesigning Combinational Logic Gates in CMOS --$tAppendix C: Layout Techniques for Complex Gates --$gCh. 5.$tVery High Performance Digital Circuits --$tAppendix D: The Schottky-Barrier Diode --$gCh. 6.$tDesigning Sequential Logic Circuits --$gCh. 7.$tDesigning Arithmetic Building Blocks --$tAppendix E: From Datapath Schematics to Layout --$gCh. 8.$tCoping with Interconnect --$gCh. 9.$tTiming Issues in Digital Circuits --$gCh. 10.$tDesigning Memory and Array Structures --$gCh. 11.$tDesign Methodologies.
650 0 $aDigital integrated circuits$xDesign and construction.$0http://id.loc.gov/authorities/subjects/sh87006329
830 0 $aPrentice Hall electronics and VLSI series.$0http://id.loc.gov/authorities/names/n96064289
852 00 $bsci$hTK7874.65$i.R33 1996
852 00 $bsci$hTK7874.65$i.R33 1996