| Record ID | marc_columbia/Columbia-extract-20221130-013.mrc:280518254:2997 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-013.mrc:280518254:2997?format=raw |
LEADER: 02997cam a2200361 a 4500
001 6335218
005 20221122023412.0
008 070329s2007 nyu b 001 0 eng
015 $aGBA725962$2bnb
016 7 $a013708899$2Uk
020 $a9780387368375 (hbk.)
020 $a038736837X (hbk.)
029 1 $aOHX$bhar075008263
035 $a(OCoLC)ocn123113658
035 $a(OCoLC)123113658
035 $a(NNC)6335218
035 $a6335218
040 $aUKM$cUKM$dOHX$dBTCTA$dBAKER$dYDXCP$dOrLoB-B
082 04 $a621.395$222
245 00 $aModern circuit placement :$bbest practices and results /$cedited by J. Cong and Gi-Joon Nam.
260 $aNew York ;$aLondon :$bSpringer,$c2007.
263 $a200706
300 $a321 pages ;$c24 cm.
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
490 1 $aSeries on integrated circuits and systems
505 00 $gPt. I.$tBenchmarks -- $g1.$tISPD 2005/2006 Placement Benchmarks -- $g2.$tLocality and Utilization in Placement Suboptimality -- $gPt. II.$tFlat Placement Techniques -- $g3.$tDPlace: Anchor Cell-Based Quadratic Placement with Linear Objective -- $g4.$tKraftwerk: A Fast and Robust Quadratic Placer Using an Exact Linear Net Model -- $gPt. III.$tTop-Down Partitioning-Based Techniques -- $g5.$tCapo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability -- $g6.$tCongestion Minimization in Modern Placement Circuits -- $gPt. IV.$tMultilevel Placement Techniques -- $g7.$tAPlace: A High Quality, Large-Scale Analytical Placer -- $g8.$tFastPlace: An Efficient Multilevel Force-Directed Placement Algorithm -- $g9.$tmFAR: Multilevel Fixed-Points Addition-Based VLSI Placement -- $g10.$tmPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control -- $g11.$tNTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs -- $g12.$tConclusion and Challenges.
520 1 $a"Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization." "Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields."--BOOK JACKET.
650 0 $aIntegrated circuit layout.$0http://id.loc.gov/authorities/subjects/sh2001008431
700 1 $aCong, Jason.$0http://id.loc.gov/authorities/names/n2002162279
700 1 $aNam, Gi-Joon.$0http://id.loc.gov/authorities/names/no2008003217
830 0 $aSeries on integrated circuits and systems.$0http://id.loc.gov/authorities/names/no2006011176
852 00 $boff,eng$hTK7874.55$i.M63 2007g