MARC Record from marc_columbia

LEADER: 07242cam a2200421Ia 4500
001 7233489
005 20221130221923.0
008 090624s2009 paua b 101 0 eng d
020 $a9781605110844
020 $a1605110841
035 $a(OCoLC)ocn407067779
035 $a(OCoLC)407067779
035 $a(NNC)7233489
035 $a7233489
040 $aLHL$cLHL$dYDXCP$dOrLoB-B
090 $aTA1637$b.M367 2008
245 00 $aMaterials and technologies for 3-D integration :$bsymposium held December 1-3, 2008, Boston, Massachusetts, U.S.A. /$ceditors: F. Roozeboom [and others].
260 $aWarrendale, Pa. :$bMaterials Research Society,$c2009.
300 $axiii, 273 pages :$billustrations ;$c24 cm.
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
490 1 $aMRS proceedings ;$vv. 1112
500 $a"... Symposium E... 2008 MRS Fall Meeting in Boston, Massachusetts" -- p. xii.
504 $aIncludes bibliographical references and index.
505 00 $t3D Process Integration - Requirements and Challenges /$rM. Juergen Wolf, Armin Klumpp, Kai Zoschke, Robert Wieland, Lars Nebrich, Matthias Klein, Hermann Oppermann, Peter Ramm, Oswin Ehrmann and Herbert Reichl -- $tThree-Dimensional Integration Technology for Advanced Focal Planes /$rCraig L. Keast, Brian Aull, James Burns, Chenson Chen, Jeff Knecht, Brian Tyrrell, Keith Warner, Bruce Wheeler, Vyshi Suntharalingam, Peter Wyatt and Donna Yost -- $tCurrent and Future 3D-LSI Technology for the Image Sensor Devices /$rMakoto Motoyoshi, Hirofumi Nakamura, Manabu Bonkohara and Mitsumasa Koyanagi -- $tScalability and Low Cost of Ownership Advantages of Direct Bond Interconnect (DBI) as Drivers for Volume Commercialization of 3D Integration Architectures and Applications /$rPaul Enquist -- $t3D Wafer Level Packaging: Processes and Materials for Through-Silicon Vias and Thin Die Embedding /$rPhilippe Soussan, Deniz Sabuncuoglu Tezcan, Francois Iker, Wouter Ruythooren, Bart Swinnen, Bivragh Majeed and Eric Beyne -- $tWafer and Die Bonding Technologies for 3D Integration /$rShari Farrens -- $t3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces /$rJian-Qiang Lu, J. J. McMahon and Ronald J. Gutmann -- $t3D Vertical Interconnects by Copper Direct Bonding /$rLea DiCioccio, Pierric Gueguen, Patrice Gergaud, Marc Zussy, Dominique Lafond, Jean Pierre Gonchond, Maurice Rivoire, Daniel Scevola and Laurent Clavelier -- $tAmbient Copper-Copper Thermocompression Bonding Using Self-Assembled Monolayers /$rXiaofang Ang, Jun Wei, Zhong Chen and Chee Cheong Wong -- $tEffect of Temperature and Bonding Duration on the Mechanical Strength of Metal-to-Metal Thermocompression Bonds /$rRiko K. Made, Chee Lip Gan and Liling Yan -- $tFabrication and Characterization of Metal-to-Metal Interconnect Structures for 3D Integration /$rAlan Huffman, John Lannon, Matthew Lueck, Christopher Gregory and Dorota Temple -- $tThree-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking /$rTakafumi Fukushima, Tetsu Tanaka and Mitsumasa Koyanagi -- $tBosch Process - DRIE Success Story, New Applications and Products /$rAndrea Urban and Franz Laermer -- $tThe Effect of Process Parameters on Electrical Properties of High Density Through-Si Vias /$rPatrick Leduc, Myriam Assous, David Bouchu, Antonio Roman, Michel Heitzmann, Barbara Charlet, Lea DiCioccio, Marc Zussy, Lucile Mage, Laurent Vandroux, Emmanuel Deronzier, Anne Roule, Paul-Henri Haumesser and Nicolas Sillon -- $tFront End of Line Through Silicon Via (TSV) Integration /$rSubhash L. Shinde, Todd M. Bauer, Jordan E. Massad and Dale L. Hetherington -- $tCu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits /$rAleksandar Radisic, Ole Luhn, Bart Swinnen, Hugo Bender, Chris Drijbooms, Geert Doumen, Kristof Kellens, Wouter Ruythooren and Philippe M. Vereecken -- $tA Method for Die Thickness Reduction to sub-35 [actual symbol not reproducible]m /$rJeffrey Thompson, Gary Tepolt, Livia Racz, Chris Rogers, Robert White and Vincent Manno -- $tStatistical Analysis of the Influence of Thinning Processes on the Strength of Silicon /$rYu Yang, Ricardo Cotrin Teixeira, Philippe Roussel, Bart Swinnen, Bert Verlinden and Ingrid De Wolf -- $tOxidized ALD-Deposited Titanium Nitride Films as a Low-Temperature Alternative for Enhancing the Wettability of Through-Silicon Via Sidewalls /$rMohamed Saadaoui, Henk van Zeijl, Mai Hoa Pham, Harm Knoops, W. M. M. Kessels, M. van de Sanden, Fred Roozeboom, Yann Lamy, K. B. Jinesh, Wim Besling and P. M. Sarro -- $tRecent Technology and Material Developments in 3D Packaging and Assembly /$rMarc de Samber, Eric van Grunsven, Verard Kums, Anton van der Lugt and Hans de Vries -- $tDie-to-Wafer 3D Integration Technology for High Yield and Throughput /$rKatsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, Yukifumi Oyama, Chirag S. Patel, Kuniaki Sueoka, Edmund J. Sprogis and John Knickerbocker -- $t3D MEMS and IC Integration /$rMaaike M. Taklo, Nicolas Lietaer, Hannah R. Tofteberg, Timo Seppanen, Josef Prainsack, Josef Weber and Peter Ramm -- $tHotspot-Optimized Interlayer Cooling in Vertically Integrated Packages /$rThomas Brunschwiler, Bruno Michel, Hugo Rothuizen, Urs Kloter, Bernhard Wunderle and Herbert Reichl -- $tDesign Support for 3D System Integration by Multi Physics Simulation /$rPeter Schneider, Sven Reitz, Joern Stolle, Roland Martin, Andreas Wilde, Peter Ramm and Josef Weber -- $tThrough Silicon Via Metalization: A Novel Approach for Insulation/Barrier/Copper Seed Layer Deposition Based on Wet Electrografting and Chemical Grafting Technologies /$rDominique Suhr, Jose Gonzalez, Isabelle Bispo, Frederic Raynal, Claudio Truzzi, Steve Lerner and Vincent Mevellec -- $tCharacterization of Texture and Microstructure of Electrodeposited Ni Layers /$rHomuro Noda, Akinobu Shibata, Masato Sone, Chiemi Ishiyama and Yakichi Higo -- $tA Novel Method for the Growth of Low Temperature Silicon Structures for 3D Flash Memory Devices /$rThomas A. Mih, Richard B. Cross and Shashi Paul.
650 0 $aComputer graphics$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2008100018
650 0 $aImage processing$xDigital techniques$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2008104266
650 0 $aThree-dimensional imaging$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2010116514
650 0 $aThree-dimensional display systems$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2008112889
650 0 $aThree-dimensional imaging$xMaterials$vCongresses.
650 0 $aThree-dimensional display systems$xMaterials$vCongresses.
650 0 $aIntegrated circuits$xWafer-scale integration$vCongresses.
650 0 $aIntegrated circuits$xMaterials$vCongresses.$0http://id.loc.gov/authorities/subjects/sh2008123904
700 1 $aRoozeboom, Fred.$0http://id.loc.gov/authorities/names/n96022716
710 2 $aMaterials Research Society.$bFall Meeting$d(2008 :$cBoston, Mass.)
711 2 $aSymposium E, "Materials and technologies for 3-D Integration"$d(2008 :$cBoston, Mass.)
830 0 $aMaterials Research Society symposia proceedings ;$vv. 1112.$0http://id.loc.gov/authorities/names/n42037756
852 00 $boff,eng$hTA1637$i.M367 2008g