MARC Record from marc_columbia

LEADER: 17388cam a2200373 a 4500
001 7992913
005 20221201051551.0
008 100405t20112011flua b 001 0 eng
010 $a 2010011811
020 $a9781439826942 (hardcover : alk. paper)
020 $a1439826943 (hardcover : alk. paper)
024 $a40018299903
035 $a(OCoLC)435419190
035 $a(OCoLC)ocn435419190
035 $a(NNC)7992913
035 $a7992913
040 $aDLC$cDLC$dYDX$dUKM$dBTCTA$dYDXCP$dCDX$dBWX$dOrLoB-B
050 00 $aTK7871.85$b.R317 2011
082 00 $a621.3815/2$222
245 00 $aRadiation effects in semiconductors /$cedited by Krzysztof Iniewski.
260 $aBoca Raton, FL :$bCRC Press,$c[2011], ©2011.
300 $axv, 415 pages :$billustrations ;$c25 cm.
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
490 1 $aDevices, circuits, and systems
504 $aIncludes bibliographical references and index.
505 00 $gSECTION I.$tDevices -- $gChapter 1.$tRadiation Damage in Silicon /$rGianluigi Casse -- $g1.1.$tIntroduction -- $g1.1.1.$tSurface Damage -- $g1.1.2.$tBulk Damage -- $g1.2.$tAnnealing of Ir and Neff -- $g1.2.1.$tImpurities in Silicon -- $g1.2.2.$tCharge Trapping and Charge Collection -- $g1.3.$tAssessing the Radiation Hardness of Silicon Detectors -- $g1.3.1.$tSilicon Detectors and High-Energy Physics Experiments: A Success Story -- $g1.3.2.$tRadiation Hardening of Silicon Detectors -- $g1.3.3.$tRadiation Tolerance of n-Side Readout Sensors -- $g1.3.4.$tEffect of Varying the Detector Thickness -- $g1.3.5.$tReverse Current in Heavily Irradiated Thin and Standard Silicon Sensors -- $g1.3.6.$tRadiation Tolerance of Different Single Crystal Silicon -- $g1.3.6.1.$tMCz Silicon -- $g1.3.6.2.$tEpitaxial Silicon -- $g1.4.$tAnnealing Effects -- $g1.5.$tConclusions: The ATLAs Example Case -- $tReferences -- $gChapter 2.$tRadiation-Tolerant CMOS Single-Photon Imagers for Multiradiation Detection /$rHerbert Shea -- $g2.1.$tIntroduction -- $g2.2.$tSolid-State-Photon-Detecting Pixels -- $g2.3.$tAPDs and SPADs Fabricated in CMOS Processes -- $g2.3.1.$tBasic Structure Design -- $g2.3.2.$tQuenching and Recharge -- $g2.3.3.$tThe Importance of Miniaturization -- $g2.4.$tBuilding and Testing Radiation-Hardened SPADs -- $tReferences -- $gChapter 3.$tEffects of Hydrogen on the Radiation Response of Field-Oxide Field-Effect Transistors and High-K Dieclectrics /$rRonald D. Schrimpf -- $g3.1.$tIntroduction -- $g3.2.$tBackground on 1/f Noise -- $g3.3.$tExperimental Details -- $g3.4.$tResults and Discussion -- $g3.4.1.$tElectrical Measurements -- $g3.4.2.$tNoise Measurements -- $g3.5.$tHigh-K Dielectrics -- $g3.6.$tSummary and Conclusions -- $tAcknowledgments -- $tReferences -- $gChapter 4.$tNovel Total Dose and Heavy-Ion Charge Collection Phenomena in a New SiGe HBT on Thin-Film SOI Technology /$rMarek Turowski -- $g4.1.$tIntroduction -- $g4.2.$tDevice Structure and Basic Operation -- $g4.3.$tIrradiation -- $g4.4.$tSimulation Study of Single-Event Upset Response -- $g4.5.$tConclusions -- $tReferences -- $gChapter 5.$tRadiation-Hard Voltage and Current References in Standard CMOS Technologies /$rAnne-Johan Annema -- $g5.1.$tIntroduction -- $g5.2.$tRadiation-Tolerant Layout Approach for Bandgap Reference Circuits -- $g5.3.$tTypical CMOS Bandgap Voltage Summing Reference -- $g5.4.$tRadiation-Hard Voltage References -- $g5.5.$tRadiation-Hard Current References -- $g5.6.$tConclusion -- $tReferences -- $gChapter 6.$tNanocrystal Memories: An Evolutionary Approach to Flash Memory Scaling and a Class of Radiation-Tolerant Devices /$rNicola Wrachien -- $g6.1.$tIntroduction -- $g6.2.$tFlash Memories -- $g6.2.1.$tFlash Memories: An Overview -- $g6.2.2.$tBasics of Flash Operations -- $g6.2.2.1.$tThe Read Operation in NOR and NAND -- $g6.2.2.2.$t"Program-Erase" Operation and Reliability -- $g6.3.$tNanocrystal Memories -- $g6.3.1.$tNanocrystal Memories: An Overview -- $g6.3.2.$tSi Nanocrystal Realization -- $g6.3.3.$tNanocrystal Memory Cell -- $g6.3.4.$tNanocrystal Process Integration in a Multimegabit Array -- $g6.4.$tRadiation Effects on Nonvolatile Memories -- $g6.4.1.$tRadiation Effects on NVM: An Overview -- $g6.4.1.1.$tPrompt Charge Loss Due to TID -- $g6.4.1.2.$tPrompt Charge Loss Due to SEE -- $g6.4.1.3.$tLong-Term Retention Capability -- $g6.4.2.$tRadiation Effects on Nanocrystal Memory Cells -- $g6.4.2.1.$tTotal Ionizing Dose Effects in Nanocrystal Memory -- $g6.4.2.2.$tSingle-Events in Nanocrystal Memory -- $g6.4.3.$tRadiation Tolerance of Nanocrystal Memory versus Floating-Gate Memories -- $g6.5.$tConclusions -- $tReferences -- $gSECTION II.$tCircuits and Systems -- $gChapter 7.$tRadiation Hardened by Design SRAM Strategies for TID and SEE Mitigation /$rLarence T. Clark -- $g7.1.$tChapter Overview -- $g7.1.1.$tEmbedded SRAMs in Integrated Circuit Design -- $g7.1.2.$tThe Radiation Space Environment and Effects -- $g7.1.3.$tChapter Outline -- $g7.2.$tRadiation Hardening -- $g7.2.1.$tTotal Ionizing Dose Effects -- $g7.2.2.$tSingle-Event Effects in SRAMs -- $g7.3.$tRadiation Hardening by Design in SRAMs -- $g7.3.1.$tSRAM Cell Read and Write Margins -- $g7.3.2.$tReverse-Body Bias -- $g7.3.3.$tRHBD SRAM Cell Design -- $g7.3.3.1.$tConventional Two-Edged Transistor Cell (Type 1) -- $g7.3.3.2.$tAnnular NMOS Access Transistor Cell (Type 2) -- $g7.3.3.3.$tPMOS Access Transistor SRAM Cell (Type 3) -- $g7.3.3.4.$tTwo-Edged NMOS Access Transistor SRAM Cell with Annular Pull-Down Transistors (Type 4) -- $g7.4.$tSNM Test Structure -- $g7.5.$tExperimental TID Testing Results -- $g7.5.1.$tImpact of VDD Bias on TID Response -- $g7.5.2.$tImpact of TID on Cell Margins -- $g7.5.3.$tType 4 Cell -- $g7.5.4.$tType 1 cell with RBB---Array Design Considerations -- $g7.5.5.$tType 1 Cell with RBB---Transistor Level Measurements -- $g7.5.6.$tTest SRAM Designs and Experiments -- $g7.5.7.$tType 1 Cell with RBB---SRAM Measurements -- $g7.5.8.$t90 nm Transistor-Level Response -- $g7.6.$tSingle-Event Effects in Unhardened SRAM -- $g7.7.$tSingle-Event Effects Mitigation -- $g7.7.1.$t130 nm SRAM Design with RBB+SC Support and SEE Mitigation -- $g7.7.2.$tSRAM Column Circuits -- $g7.7.3.$tSRAM Operation with RBB+SC -- $g7.7.4.$tExperimental SEE Measurements -- $g7.8.$tSummary and Conclusions -- $tReferences -- $gChapter 8.$tA Complete Guide to Multiple Upsets in SRAMs Processed in Decananometric CMOS Technologies /$rPhillippe Roche -- $g8.1.$tIntroduction -- $g8.2.$tDetails on the Experimental Setup -- $g8.2.1.$tNote on the Importance of Test Algorithm for Counting Multiple Upsets -- $g8.2.2.$tTest Facility -- $g8.2.2.1.$tAlpha Source -- $g8.2.2.2.$tNeutron Facilities -- $g8.2.2.3.$tHeavy-Ion Facilities -- $g8.2.2.4.$tProton Facility -- $g8.2.3.$tTested Devices -- $g8.3.$tExperimental Results -- $g8.3.1.$tMCU as a Function of Radiation Source -- $g8.3.2.$tMCU as a Function of Well Engineering: Triple-Well Usage -- $g8.3.3.$tMCU as a Function of Tilt Angle during Heavy-Ion Experiments -- $g8.3.4.$tMCU as a Function of Technology Feature Size -- $g8.3.5.$tMCU as a Function of Design: Well Tie Density -- $g8.3.6.$tMCU as a Function of Supply Voltage -- $g8.3.7.$tMCU as a Function of Temperature -- $g8.3.8.$tMCU as a Function of Bit Cell Architecture -- $g8.3.9.$tMCU as a Function of Test Location LANSCE versus TRIUMF -- $g8.3.10.$tMCU as a Function of Substrate: Bulk versus SOI -- $g8.3.11.$tMCU as a Function of Test Pattern -- $g8.4.$t3-D TCAD Modeling of MCU Occurrence -- $g8.4.1.$tBipolar Effect in Technologies with Triple Well -- $g8.4.1.1.$tStructures Whose Well Ties Are Located Close to the SRAM -- $g8.4.1.2.$tStructures Whose Well Ties Are Located far from the SRAM -- $g8.4.2.$tA Refined Sensitive Area for Advanced Technologies -- $g8.4.2.1.$tSimulation of Two SRAM Bit Cells in a Row -- $g8.4.2.2.$tSimulation of Two SRAM Bit Cells in a Column -- $g8.4.2.3.$tConclusions and SRAM Sensitive Area Cartography -- $g8.5.$tGeneral Conclusion: Sorting of Parameters Driving MCU Sensitivity -- $g8.5.1.$tExperimental Results in 130 nm Technology -- $g8.6.$tAnnex 1 -- $tReferences -- $gChapter 9.$tReal-Time Soft Error Rate Characterization of Advanced SRAMs /$rSebastien Sauze -- $g9.1.$tIntroduction -- $g9.2.$tTest Platforms and Environments -- $g9.2.1.$tThe ASTEP Platform -- $g9.2.2.$tThe LSM Laboratory -- $g9.3.$tExperimental Details -- $g9.3.1.$tTested Devices -- $g9.3.2.$tHardware Setups -- $g9.3.3.$tTest Procedure -- $g9.4.$tExperimental Results -- $g9.4.1.$tReal-Time Measurements -- $g9.4.2.$tAccelerated Tests -- $g9.5.$tData Analysis and Discussion -- $g9.5.1.$tReal-Time versus Accelerated Tests for 65 nm -- $g9.5.2.$t65 nm versus 130 nm Technologies -- $g9.5.3.$tEstimation of the Alpha Particle Emission Rates for 65 nm and 130 nm Technologies -- $g9.5.4.$tSynthesis and SER Trends -- $g9.6.$tConclusion -- $tAcknowledgments -- $tReferences -- $gChapter 10.$tFault Tolerance Techniques and reliability Modeling for SRAM-Based FPGAs /$rMichael Wirthlin -- $g10.1.$tIntroduction -- $g10.1.1.$tOrganization -- $g10.2.$tFPGA Radiation Effects -- $g10.2.1.$tNondestructive Single-Event Effects --
505 80 $g10.2.2.$tNondestructive Single-Event Effects -- $g10.2.2.1.$tSingle-Event Upsets -- $g10.2.2.2.$tSingle-Event Transients -- $g10.2.2.3.$tSingle-Event Functional Interrupts -- $g10.2.3.$tSEEs in FPGAs -- $g10.3.$tSEEs in FPGAs -- $g10.3.1.$tScrubbing -- $g10.3.2.$tDuplication with Comparison -- $g10.4.$tSEU-Induced Error Mitigation Techniques -- $g10.4.1.$tTriple Modular Redundancy -- $g10.4.1.1.$tPartial TMR -- $g10.4.2.$tTemporal Redundancy -- $g10.4.3.$tState Machine Encoding -- $g10.4.4.$tQuadded Logic -- $g10.5.$tReliability Model -- $g10.5.1.$tEstimating Upsets per Scrub Cycle, P(Ai) -- $g10.5.2.$tEstimating Probability of Design Failure, P(Fs/Ai) -- $g10.5.3.$tCase Study -- $g10.6.$tConclusion -- $tAcknowledgments -- $tReferences -- $gChapter 11.$tAssuring Robust Triple Modular Redundancy Protected Circuits in SRAM-Based FPGAs /$rHeather Quinn -- $g11.1.$tIntroduction -- $g11.2.$tOverview of SEU and MBU Data for FPGAs -- $g11.3.$tTMR Protection of FPGA Circuits -- $g11.3.1.$tCircuit Design Problems -- $g11.3.2.$tDevice Constraint Problems -- $g11.3.3.$tCircuit Implementation and Architectural Problems -- $g11.4.$tDomain Crossing Errors -- $g11.4.1.$tTest Methodology and Setup -- $g11.4.1.1.$tTest Circuits -- $g11.4.1.2.$tFault Inject Test Methodology -- $g11.4.1.3.$tAccelerator Test Methoodology -- $g11.4.2.$tFault Injection and Accelerator Test Results -- $g11.4.3.$tDiscussion of Results -- $g11.4.3.1.$tDCE Characteristics -- $g11.4.3.2.$tArchitectural Concerns -- $g11.4.3.3.$tVoting and Device Use -- $g11.4.3.4.$tDesign Sensitivity -- $g11.4.3.5.$tProbability of DCEs -- $g11.5.$tDetection of Single-Bit Upsets, Multiple-Bit Upsets, and Design Problems -- $g11.5.1.$tRelated Work -- $g11.5.2.$tSTARC Overview -- $g11.5.3.$tCase Study: Tradespace of Reliability Issues under Area Constraints -- $tConclusions -- $tReferences -- $gChapter 12.$tSEU/SET Tolerant Phase-Locked Loops /$rRobert L. Shuler, Jr. -- $g12.1.$tIntroduction -- $g12.2.$tVoting Asynchronous Signals -- $g12.3.$tStable PLLs that Minimize Phase-Induced Voting Error -- $g12.4.$tSEU/SET Characteristics of PLL Building Blocks -- $g12.4.1.$tRing VCO -- $g12.4.2.$tFrequency Divider -- $g12.4.3.$tSigma-Delta Fractional-n Frequency Dividers -- $g12.4.4.$tPhase-Frequency Detector -- $g12.4.5.$tCharge Pumps -- $g12.4.6.$tLoop Filter -- $g12.5.$tApplying Redundancy to PLLs -- $g12.5.1.$tOutput-Only Voting Method -- $g12.5.2.$tThe VCO Voting Method -- $g12.6.$tConclusions -- $tReferences -- $gChapter 13.$tAutonomous Detection and Characterization of Radiation-Induced Transients in Semiconductor Integrated Circuits /$rArthur F. Witulski -- $g13.1.$tIntroduction -- $g13.1.1.$tSoft Errors -- $g13.2.$tSingle-Event Transients and Logic Soft Errors -- $g13.2.1.$tSingle Events in Logic Circuits -- $g13.2.2.$tLogic Soft Errors---Scaling Trends -- $g13.2.3.$tPrevious SET Characterization -- $g13.3.$tAutonomous Pulse-Width Characterization -- $g13.3.1.$tPropagation of a Transient through a Series of Inverters -- $g13.3.2.$tSelf-Triggered Transient Capture -- $g13.3.3.$tPulse Capture Circuit Design -- $g13.3.4.$tIllustration of Pulse Capture -- $g13.3.5.$tTest Chip Designs -- $g13.4.$tHeavy-Ion Test Results -- $g13.4.1.$tHeavy-Ion Tests, 130 nm -- $g13.4.1.$tHeavy-Ion 90 nm -- $g13.4.3.$tTechnology Scaling Trends Based on Heavy-ion Experimental Results -- $g13.5.$tNeutron and Alpha Particle Induced Transients -- $g13.5.1.$tNeutron Induced SET Pulse Widths -- $g13.5.2.$tAlpha Particle Induced SET Pulse Widths -- $g13.5.3.$tNeutron and Alpha FIT Rates -- $g13.6.$tSummary -- $tReferences -- $gChapter 14.$tSoft Errors in Digital Circuits: Overview and Protection Techniques for Digital Filters /$rJuan Antonio Maestro -- $g14.1.$tIntroduction -- $g14.2.$tRadiation Effects on Electronic Devices -- $g14.2.1.$tNondestructive Failures -- $g14.2.2.$tDestructive Failures -- $g14.2.3.$tCumulative Failures -- $g14.3.$tMethodologies to Predict the Behavior of Integarated Circuits in the Presence of Soft Errors -- $g14.3.1.$tSimulation-Based Fault Injection (SBFI) -- $g14.3.2.$tHardware Fault Injection (HWFI) -- $g14.3.3.$tSoftware Implementation Fault Injection (SWIFI) -- $g14.3.4.$tTechniques Based on Hybrid Models: Hardware Emulation -- $g14.4.$tTechniques to Provide Fault Tolerance in Electronic Devices: Radiation Hardening -- $g14.4.1.$tProcess to Reduce the Charge Generation and Accumulation -- $g14.4.2.$tMitigation of Set Generation and Propagation -- $g14.5.$tTechniques to Provide Fault Tolerance in Electronic Devices -- $g14.5.1.$tSpatial Redundancy -- $g14.5.2.$tTemporal Redundancy -- $g14.5.3.$tInformation Redundancy -- $g14.6.$tAd Hoc Protection Techniques for Digital Filters -- $g14.6.1.$tFirst Scenario (Low Protection Requirements) -- $g14.6.2.$tSecond Scenario (Average Protection Requirements) -- $g14.6.3.$tThird Scenario (High Protection Requirements) -- $g14.6.4.$tEvaluation of the Protection Techniques -- $g14.6.5.$tComparison with TMR -- $g14.7.$tConclusions -- $tReferences -- $gChapter 15.$tFault-Injection Techniques for Dependability Analysis: An Overview /$rMassimo Violante -- $g15.1.$tIntroduction -- $g15.2.$tOverview of a Fault-Injection System -- $g15.3.$tSimulation-Based Fault Injection -- $g15.3.1.$tAn Example of Fault Injection Using System-Level Simulation -- $g15.3.2.$tAn Example of Fault Injection Using Register-Transfer-Level Simulation -- $g15.3.3.$tFinal Remarks on Simulation-Based Fault Injection -- $g15.4.$tEmulation-Based Fault Injection -- $g15.4.1.$tAn Example of Emulation-Based Fault Injection -- $g15.4.2.$tFinal Remarks on Emulation-Based Fault Injection -- $g15.5.$tSoftware-Based Fault Injection -- $g15.5.1.$tAn Example of Software-Implemeted Fault Injection -- $g15.5.2.$tFinal Remarks on Software-Implemented Fault Injection -- $g15.6.$tConclusions -- $tAcknowledgment -- $tReferences.
520 1 $a"Space applications, nuclear physics, military operations, medical imaging, and especially electronics (modern silicon processing) are obvious fields in which radiation damage can have serious consequences, i.e., degradation of MOS devices and circuits. Zeroing in on vital aspects of this broad and complex topic, Radiation Effects in Semiconductors addresses the evergrowing need for a clear understanding of radiation effects on semiconductor devices and circuits to combat any potential damage it can cause." "This book analyzes the radiation problem, focusing on the most important aspects required for comprehending the degrading effects observed in semiconductor devices, circuits, and Systems when they are irradiated. It explores how radiation interacts with solid materials, and it provides a detailed analysis of three ways this occurs: photoelectric effect. Compton effect, and creation f electron-positron pairs. The author explains that the probability of these three effects occurring depends on the energy of the incident photon and the atomic number of the target. The book also discusses the effects that photons can have on matter---in terms of ionization effects and nuclear displacement." "Aimed at post-graduate researchers, semiconductor engineers, and nuclear and Space engineers with some electronics background, this carefully construted reference explains how ionizing radiation is creating damage in semiconducting devices and circuits and systems---and how that damage can be avoided in areas such as military/space missions, nuclear applications, plasma damage, and X-ray-based techniques. It features top-notch international experts in industry and academia who address emerging detector technologies, circuit design techniques, new materials, and innovative system appraches. This book is a must-read for anyone serious about understanding radiation effects in the electronics industry."--BOOK JACKET.
650 0 $aSemiconductors$xEffect of radiation on.$0http://id.loc.gov/authorities/subjects/sh85119909
650 0 $aPhoton emission.$0http://id.loc.gov/authorities/subjects/sh93001219
700 1 $aIniewski, Krzysztof,$d1960-$0http://id.loc.gov/authorities/names/n2007019278
830 0 $aDevices, circuits, and systems.$0http://id.loc.gov/authorities/names/no2010004727
852 00 $boff,eng$hTK7871.85$i.R317 2011