MARC Record from marc_columbia

LEADER: 03453cam a2200397Ii 4500
001 13501991
005 20181022143215.0
008 170424t20192019maua b 001 0 eng d
019 $a983678310
020 $a0128119055$q(pbk.)
020 $a9780128119051$q(pbk.)
035 $a(OCoLC)ocn983459758
035 $a(OCoLC)983459758$z(OCoLC)983678310
035 $a(NNC)13501991
040 $aYDX$beng$erda$cYDX$dIMN$dFQG$dMEAUC$dMYG$dTXI$dWCM$dUAB$dNRC
050 4 $aQA76.9.A73$bP377 2019
082 04 $a004.2/2$223
100 1 $aHennessy, John L.,$eauthor.
245 10 $aComputer architecture :$ba quantitative approach /$cJohn L. Hennessy (Stanford University), David A. Patterson (University of California, Berkeley) ; with contributions by Krste Asanović [and 16 others].
250 $aSixth edition.
264 1 $aCambridge, MA :$bMorgan Kaufmann Publishers, an imprint of Elsevier,$c[2019]
264 4 $c©2019
300 $axxix, 617 pages, 284 pages in various pagings :$billustrations ;$c24 cm
336 $atext$btxt$2rdacontent
336 $astill image$bsti$2rdacontent
337 $aunmediated$bn$2rdamedia
338 $avolume$bnc$2rdacarrier
504 $aIncludes bibliographical references (pages R1-R36) and index.
520 $aComputer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
505 0 $aFundamentals of quantitative design and analysis -- Memory hierarchy design -- Instruction-level parallelism and its exploitation -- Data-level parallelism in vector, SIMD, and GPU architectures -- Thread-level parallelism -- Warehouse-scale computers to exploit request-level and data-level parallelism -- Domain-specific architectures -- Appendix A. Instruction set principles ; Appendix B. Review of memory hierarchy ; Appendix C. Pipelining : basic and intermediate concepts -- Online appendices. Appendix D. Storage systems ; Appendix E. Embedded systems ; Appendix F. Interconnection networks ; Appendix G. Vector processors in more depth ; Appendix H. Hardware and software for VLIW and EPIC ; Appendix I. Large-scale multiprocessors and scientific applications ; Appendix J. Computer arithmetic ; Appendix K. Survey of instruction set architectures ; Appendix L. Advanced concepts on address translation ; Appendix M. Historical perspectives and references.
650 0 $aComputer architecture.
650 7 $aComputer architecture.$2fast$0(OCoLC)fst00872026
650 4 $aComputer architecture.$0(OCoLC)fst00872026
700 1 $aPatterson, David A.,$eauthor.
700 1 $aAsanović, Krste,$eauthor.
852 00 $bsci$hQA76.9.A73$iP377 2019