| Record ID | marc_columbia/Columbia-extract-20221130-031.mrc:221632661:3079 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-031.mrc:221632661:3079?format=raw |
LEADER: 03079cam a2200613 i 4500
001 15120384
005 20220618232657.0
006 m o d
007 cr cnu---unuuu
008 170629s2017 flu ob 000 0 eng d
035 $a(OCoLC)ocn992167435
035 $a(NNC)15120384
040 $aN$T$beng$erda$epn$cN$T$dYDX$dMERUC$dUIU$dCRCPR$dIDEBK$dOCLCQ$dUAB$dMERER$dOCLCQ$dUPM$dERL$dSTF$dCNCGM$dOCLCQ$dNLE$dUKMGB$dWYU$dK6U$dOCLCO$dOCLCQ$dNRC$dOCLCO
015 $aGBB7B7246$2bnb
016 7 $a018403698$2Uk
020 $a9781351751049$q(electronic bk.)
020 $a1351751042$q(electronic bk.)
020 $a9781315191089$q(electronic)
020 $a1315191083
020 $a9781315191089
020 $a9781498783606
020 $a1498783600
020 $z9781498783590
020 $z1498783597
035 $a(OCoLC)992167435
037 $a9781351751049$bIngram Content Group
050 4 $aTK7871.95$b.D37 2017eb
072 7 $aTEC$x009070$2bisacsh
082 04 $a621.3815/284$223
049 $aZCUA
100 1 $aDasgupta, Sudeb,$eauthor.
245 10 $aSpacer engineered FinFET architectures :$bhigh-performance digital circuit applicators /$cSudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal.
264 1 $aBoca Raton :$bTaylor & Francis, CRC Press,$c2017.
300 $a1 online resource
336 $atext$btxt$2rdacontent
337 $acomputer$bc$2rdamedia
338 $aonline resource$bcr$2rdacarrier
504 $aIncludes bibliographical references.
505 0 $aIntroduction to nanoelectronics -- Tri-gate FinFET technology and its advancement -- Dual-K spacer device architectures and its electrostatics -- Capacitive analysis & dual-K FinFET based digital circuit design -- Design metric improvement of dual-K based SRAM cell -- Statistical variability & sensitivity analysis.
588 0 $aPrint version record.
520 3 $aThis book focusses on the spacer engineering aspects of novel MOS-based device circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
650 0 $aMetal oxide semiconductor field-effect transistors.
650 0 $aSilicon-on-insulator technology.
650 6 $aTransistors MOSFET.
650 6 $aSilicium sur isolant.
650 7 $aTECHNOLOGY & ENGINEERING$xMechanical.$2bisacsh
650 7 $aMetal oxide semiconductor field-effect transistors.$2fast$0(OCoLC)fst01017614
650 7 $aSilicon-on-insulator technology.$2fast$0(OCoLC)fst01118704
655 4 $aElectronic books.
700 1 $aKaushik, Brajesh Kumar,$eauthor.
700 1 $aPal, Pankaj Kumar,$eauthor.
776 08 $iPrint version:$aDasgupta, Sudeb.$tSpacer engineered FinFET architectures.$dBoca Raton : Taylor & Francis, CRC Press, 2017$z9781498783590$w(DLC) 2016051118$w(OCoLC)975270243
856 40 $uhttp://www.columbia.edu/cgi-bin/cul/resolve?clio15120384$zTaylor & Francis eBooks
852 8 $blweb$hEBOOKS