| Record ID | marc_loc_2016/BooksAll.2016.part21.utf8:187484456:929 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_2016/BooksAll.2016.part21.utf8:187484456:929?format=raw |
LEADER: 00929cam a2200253 a 4500
001 92008800
003 DLC
005 19991015104817.0
008 920221s1992 maua b 001 0 eng
010 $a 92008800
020 $a0890065802
040 $aDLC$cDLC$dDLC
050 00 $aTK7888.4$b.R35 1992
082 00 $a621.39/5/0287$220
100 1 $aRajsuman, Rochit.
245 10 $aDigital hardware testing :$btransistor-level fault modeling and testing /$cRochit Rajsuman.
260 $aBoston :$bArtech House,$cc1992.
300 $axv, 317 p. :$bill. ;$c24 cm.
440 0 $aArtech House telecommunications library
500 $a"Annotated bibliography": p. 303-310.
504 $aIncludes bibliographical references and index.
650 0 $aElectronic digital computers$xCircuits$xTesting$xData processing.
650 0 $aIntegrated circuits$xVery large scale integration$xTesting$xData processing.
650 0 $aElectric fault location.