| Record ID | marc_loc_2016/BooksAll.2016.part28.utf8:227026560:1161 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_2016/BooksAll.2016.part28.utf8:227026560:1161?format=raw |
LEADER: 01161cam a22003014a 4500
001 2001050273
003 DLC
005 20080312083915.0
008 010919s2001 ne a b 001 0 eng
010 $a 2001050273
020 $a1402000898 (alk. paper)
040 $aDLC$cDLC$dDLC
042 $apcc
050 00 $aTK7874.75$b.L8 2001
082 00 $a621.39/5$221
100 1 $aLu, Bing.
245 10 $aLayout optimizations in VLSI designs /$cBing Lu, Ding-Zhu Du, Sachin S. Sapatnekar.
260 $aDordrecht ;$aBoston :$bKluwer Academic Publishers,$c2001.
300 $aviii, 288 p. :$bill. ;$c25 cm.
440 0 $aNetwork theory and applications ;$vv. 8
504 $aIncludes bibliographical references.
650 0 $aIntegrated circuits$vVery large scale integration$xDesign and construction.
650 0 $aMultidisciplinary design optimization.
650 0 $aIntegrated circuit layout.
700 1 $aDu, Dingzhu.
700 1 $aSapatnekar, Sachin S.,$d1967-
856 42 $3Publisher description$uhttp://www.loc.gov/catdir/enhancements/fy0822/2001050273-d.html
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/enhancements/fy0822/2001050273-t.html