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MARC Record from Library of Congress

Record ID marc_loc_2016/BooksAll.2016.part37.utf8:170679266:2824
Source Library of Congress
Download Link /show-records/marc_loc_2016/BooksAll.2016.part37.utf8:170679266:2824?format=raw

LEADER: 02824cam a22003134a 4500
001 2010048032
003 DLC
005 20150413182734.0
008 101215s2011 enka b 001 0 eng
010 $a 2010048032
020 $a9780470685716 (hardback)
020 $a0470685719 (hardback)
035 $a(OCoLC)ocn682892492
040 $aDLC$cDLC$dYDX$dBTCTA$dYDXCP$dDLC
042 $apcc
050 00 $aTK7871.85$b.V6525 2011
082 00 $a621.3815/2$222
084 $aTEC008010$2bisacsh
100 1 $aVoldman, Steven H.
245 10 $aESD.$pDesign and synthesis /$cSteven H. Voldman.
260 $aChichester, West Sussex, U.K. :$bWiley,$c2011.
300 $axx, 270 p. :$bill. ;$c25 cm.
504 $aIncludes bibliographical references and index.
520 $a"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"--$cProvided by publisher.
520 $a"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip"--$cProvided by publisher.
650 0 $aSemiconductors$xProtection.
650 0 $aIntegrated circuits$xProtection.
650 0 $aElectrostatics.
650 0 $aAnalog electronic systems$xDesign and construction.