| Record ID | marc_loc_2016/BooksAll.2016.part38.utf8:153863781:1200 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_2016/BooksAll.2016.part38.utf8:153863781:1200?format=raw |
LEADER: 01200cam a2200313 a 4500
001 2010935810
003 DLC
005 20121107081848.0
008 100826s2011 nyua b 001 0 eng d
010 $a 2010935810
020 $a9781441969101
020 $a1441969101
035 $a(OCoLC)ocn646114151
040 $aBTCTA$beng$cBTCTA$dYDXCP$dCDX$dIUA$dNDD$dDLC
042 $alccopycat
050 00 $aTK5105.546$b.L69 2011
082 04 $a621.3815/31$222
245 00 $aLow power networks-on-chip /$cCristina Silvano, Marcello Lajolo, Gianluca Palermo, editors.
260 $aNew York :$bSpringer Verlag ;$cc2011.
300 $axix, 287 p. :$bill. ;$c25 cm.
500 $aIncludes index.
505 0 $apt. 1. Low-level design techniques -- pt. 2. System-level design techniques -- pt. 3. Future and emerging technologies.
650 0 $aNetworks on a chip.
650 0 $aLow voltage integrated circuits.
700 1 $aSilvano, Cristina.
700 1 $aLajolo, Marcello.
700 1 $aPalermo, Gianluca.
856 42 $3Publisher description$uhttp://www.loc.gov/catdir/enhancements/fy1304/2010935810-d.html
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/enhancements/fy1304/2010935810-t.html