| Record ID | marc_loc_updates/v35.i26.records.utf8:12707364:1047 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_updates/v35.i26.records.utf8:12707364:1047?format=raw |
LEADER: 01047cam a22002778a 4500
001 2007023373
003 DLC
005 20070620101331.0
008 070604s2007 ne b 001 0 eng
010 $a 2007023373
020 $a9780123739735 (hardcover : alk. paper)
040 $aDLC$cDLC$dDLC
050 00 $aTK7895.E42$bS978 2007
082 00 $a621.39/5$222
245 00 $aSystem-on-chip test architectures :$bnanometer design for testability /$cedited by Laung-Terng Wang, Charles Stroud, and Nur Touba.
260 $aAmsterdam ;$aBoston :$bMorgan Kaufmann Publishers,$c2007.
263 $a0711
300 $ap. cm.
504 $aIncludes bibliographical references and index.
650 0 $aSystems on a chip$xTesting.
650 0 $aIntegrated circuits$xVery large scale integration$xTesting.
650 0 $aIntegrated circuits$xVery large scale integration$xDesign.
700 1 $aWang, Laung-Terng.
700 1 $aStroud, Charles E.
700 1 $aTouba, Nur.
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/toc/ecip0719/2007023373.html