| Record ID | marc_loc_updates/v36.i10.records.utf8:24349482:1414 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_updates/v36.i10.records.utf8:24349482:1414?format=raw |
LEADER: 01414cam a22003257a 4500
001 2005938214
003 DLC
005 20080307083901.0
008 051205s2006 nyua b 001 0 eng d
010 $a 2005938214
016 7 $a977544923$2GyFmDB
020 $a0387292217
024 3 $a9780387292212
035 $a(CStRLIN)PASGA3145095-B
035 $a(PSt) (Sirsi) a3145095
040 $aOHX$cOHX$dNIC$dDLC
042 $alccopycat
050 00 $aTK7885.7$b.B48 2006
082 00 $a621.39/2$222
100 1 $aBergeron, Janick.
245 10 $aWriting testbenches using System Verilog /$cby Janick Bergeron.
260 $aNew York :$bSpringer,$cc2006.
300 $axxvi, 412 p. :$bill. ;$c25 cm.
500 $aThis book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
504 $aIncludes bibliographical references and index.
650 0 $aComputer hardware description languages.
650 0 $aIntegrated circuits$xVerification.
700 1 $aBergeron, Janick.$tWriting testbenches, functional verification of HDL models.
856 42 $3Publisher description$uhttp://www.loc.gov/catdir/enhancements/fy0663/2005938214-d.html
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/enhancements/fy0814/2005938214-t.html