| Record ID | marc_loc_updates/v37.i09.records.utf8:3988686:1128 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_updates/v37.i09.records.utf8:3988686:1128?format=raw |
LEADER: 01128cam a2200301 a 4500
001 2007030307
003 DLC
005 20090227151821.0
008 070720s2008 njua b 001 0 eng
010 $a 2007030307
020 $a0132365049 (hbk. : alk. paper)
020 $a9780132365048 (hbk. : alk. paper)
035 $a(OCoLC)ocn156831239
035 $a(OCoLC)156831239
040 $aDLC$cDLC$dBTCTA$dBAKER$dYDXCP$dC#P$dDLC
050 00 $aTK7874.65$b.E36 2008
082 00 $a621.3815$222
100 1 $aEdlund, Greg.
245 10 $aTiming analysis and simulation for signal integrity engineers /$cGreg Edlund.
260 $aUpper Saddle River, NJ :$bPrentice Hall,$cc2008.
300 $axx, 241 p. :$bill. ;$c25 cm.
440 0 $aPrentice Hall modern semiconductor design series
500 $a"Prentice Hall signal integrity library"--Cover.
504 $aIncludes bibliographical references (p. 233-234) and index.
650 0 $aTiming circuits$xDesign and construction.
650 0 $aDigital electronics$xDesign and construction.
650 0 $aSignal processing$xDigital techniques.
650 0 $aSignal integrity (Electronics)