| Record ID | marc_loc_updates/v37.i35.records.utf8:61785882:1091 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_updates/v37.i35.records.utf8:61785882:1091?format=raw |
LEADER: 01091cam a2200289 a 4500
001 2008026558
003 DLC
005 20090827090726.0
008 080616s2009 flua b 001 0 eng
010 $a 2008026558
020 $a9781420044713 (hardback : alk. paper)
020 $a1420044710 (hardback : alk. paper)
035 $a(OCoLC)ocn144523940
035 $a(OCoLC)144523940
040 $aDLC$cDLC$dBTCTA$dBAKER$dYDXCP$dC#P$dBWX$dCDX$dDLC
050 00 $aTK5105.546$b.D47 2009
082 00 $a004.1$222
245 00 $aDesign of cost-efficient interconnect processing units :$bSpidergon STNoC /$cMarcello Coppola ... [et al.].
260 $aBoca Raton :$bCRC Press,$cc2009.
300 $axxi, 263 p. :$bill. ;$c25 cm. +$e1 CD-ROM (4 3/4 in.).
440 0 $aSystem-on-chip design and technologies
504 $aIncludes bibliographical references (p. 235-261) and index.
650 0 $aNetworks on a chip.
610 20 $aST Microelectronics.
650 0 $aMicroprocessors.
700 1 $aCoppola, Marcello.
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/toc/fy0903/2008026558.html