MARC Record from Library of Congress

LEADER: 02261nam a22003858a 4500
001 2012003493
003 DLC
005 20120125142226.0
006 m |o d |
007 cr_|||||||||||
008 120125s2012 nju ob 001 0 eng
010 $a 2012003493
020 $a9781118309445 (mobi)
020 $a9781118309469 (pdf)
020 $a9781118309575 (epub)
020 $z9781118011034 (hardback)
040 $aDLC$beng$cDLC
042 $apcc
050 10 $aTK7895.E42
082 00 $a006.2/2$223
084 $aTEC008010$2bisacsh
100 1 $aChu, Pong P.,$d1959-
245 10 $aEmbedded SoPC system with Altera NIOSII processor and Verilog examples$h[electronic resource] /$cPong P. Chu.
260 $aHoboken, N.J. :$bWiley,$cc2012.
263 $a1205
300 $a1 online resource.
504 $aIncludes bibliographical references and index.
520 $a"This book explores the unique hardware programmability of FPGA (field-programmable gate array)-based embedded systems, using a learning-by-doing approach to introduce the concepts and techniques for embedded SoPC (system on a programmable chip) systems with Verilog. The book contains a large number of practical examples to illustrate and reinforce the hardware and software design concepts and techniques, as well as a complete code listing and experiment problems. The book is designed for upper-level undergraduate and entry-level graduate students in computer engineering, as well as practicing engineers"--$cProvided by publisher.
520 $a"The book utilizes FPGA devices, Nios II soft-core processor, and development platform from Altera Co., which is one of the two main FPGA manufactures"--$cProvided by publisher.
588 $aDescription based on print version record and CIP data provided by publisher; resource not viewed.
650 0 $aEmbedded computer systems.
650 0 $aField programmable gate arrays.
650 0 $aVerilog (Computer hardware description language)
650 7 $aTECHNOLOGY & ENGINEERING / Electronics / Circuits / General.$2bisacsh
776 08 $iPrint version:$aChu, Pong P., 1959-$tEmbedded SoPC system with Altera NIOSII processor and Verilog examples$dHoboken, N.J. : Wiley, c2012$z9781118011034 (hardback)$w(DLC) 2011048946