MARC Record from Library of Congress

LEADER: 02108nam a22003614a 4500
001 2007926182
003 DLC
005 20120612102134.0
008 070403s2007 nyua b 001 0 eng c
010 $a 2007926182
015 $aGBA725962$2bnb
016 7 $a013708899$2Uk
020 $a9780387368375 (hbk. : acid-free paper)
020 $a038736837X (hbk. : acid-free paper)
020 $a1441942319
020 $a9781441942319
035 $a(OCoLC)ocn123113658
040 $aCOO$cCOO$dUKM$dOHX$dBTCTA$dBAKER$dYDXCP$dIXA$dVRC$dSTF$dDEBBG$dDLC
042 $apcc
084 $aZN 4950$2rvk
050 00 $aTK7874.55$b.M63 2007
245 00 $aModern circuit placement :$bbest practices and results /$c[editors], Gi-Joon Nam, Jason Cong.
260 $aNew York :$bSpringer,$cc2007.
300 $axx, 321 p. :$bill. ;$c24 cm.
490 1 $aSeries on integrated circuits and systems
504 $aIncludes bibliographical references and index.
505 0 $aBenchmarks : ISPD 2005/2006 placement benchmarks -- Locality and utilization in placement suboptimality -- Flat placement techniques : DPlace : anchor cell-based quadratic placement with linear objective -- Kraftwerk : a fast and robust quadratic placer using an exact linear net model -- Top-down partitioning-based techniques : Capo : congestion-driven placement for standard-cell and RTL netlists with incremental capability -- Congestion minimization in modern placement circuits -- Multilevel placement techniques : APlace : a high quality, large-scale analytical placer -- FastPlace : an efficient multilevel force-directed placement algorithm -- mFAR : multilevel fixed-points addition-based VLSI placement -- mPL6 : enhanced multilevel mixed-size placement with congestion control -- NTUplace3 : an analytical placer for large-scale mixed-size designs -- Conclusion and challenges.
650 0 $aIntegrated circuit layout.
650 0 $aIntegrated circuits$xVery large scale integration.
650 07 $aIntegrierte Schaltung.$2swd
700 1 $aCong, Jason.
700 1 $aNam, Gi-Joon.
830 0 $aSeries on integrated circuits and systems.