| Record ID | marc_miami_univ_ohio/allbibs0217.out:1187832:1364 |
| Source | Miami University of Ohio |
| Download Link | /show-records/marc_miami_univ_ohio/allbibs0217.out:1187832:1364?format=raw |
LEADER: 01364cam 2200313 a 4500
001 ocn140109577
005 20080131000000.0
008 070604s2008 ne a b 001 0 eng
010 $a2007023373
020 $a9780123739735 (hardcover : alk. paper)
020 $a012373973X (hardcover : alk. paper)
040 $aDLC$cDLC$dBAKER$dBTCTA$dYDXCP$dC#P$dIXA
049 $aMIAS
050 00 $aTK7895.E42$bS978 2008
245 00 $aSystem-on-chip test architectures :$bnanometer design for testability /$cedited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
260 $aAmsterdam ;$aBoston :$bMorgan Kaufmann Publishers,$cc2008
300 $axxxvi, 856 p. :$bill. ;$c25 cm
440 4 $aThe Morgan Kaufmann series in systems on silicon
504 $aIncludes bibliographical references and index
650 0 $aSystems on a chip$xTesting
650 0 $aIntegrated circuits$xVery large scale integration$xTesting
650 0 $aIntegrated circuits$xVery large scale integration$xDesign
700 1 $aWang, Laung-Terng
700 1 $aStroud, Charles E
700 1 $aTouba, Nur A
907 $a.b37800152$b02-21-08$c02-01-08
998 $ascl$b02-11-08$cm$da$e-$feng$gne $h0$i0
947 $arts
945 $g1$i35054030634865$j0$lscli $nreceipt time 02-11-2008/6/3:24:35 PM/3:24:38 PM/3:25:37 PM/3:25:40 PM $o-$p$0.00$q-$r-$s-$t0$u1$v0$w0$x0$y.i45144266$z02-11-08