MARC Record from marc_nuls

LEADER: 09626cam 2200457Ia 4500
001 9922197440001661
005 20161129155330.0
008 060804s2006 gw a b 101 0 eng d
010 $a 2006929859
020 $a354036708X (pbk.)
024 3 $a9783540367086
029 0 $aOHX$bhar065015070
029 1 $aYDXCP$b2469321
035 $a(CSdNU)u286056-01national_inst
035 $a(OCoLC)70841017
035 $a(OCoLC)70841017
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049 $aCNUM
072 7 $aQA$2lcco
090 $aQA76.9.A3$bA73 2006
111 2 $aARC 2006$d(2006 :$cDelft, Netherlands)
245 10 $aReconfigurable computing :$barchitectures and applications : second international workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 : revised selected papers /$cKoen Bertels, Joao M.P. Cardoso, Stamatis Vassiliadis (eds.).
246 30 $aARC 2006
260 $aBerlin ;$aNew York :$bSpringer,$cc2006.
300 $axvi, 469 p. :$bill. ;$c24 cm.
440 0 $aLecture notes in computer science,$x0302-9743 ;$v3985
504 $aIncludes bibliographical references and index.
505 0 $aImplementation of realtime and highspeed phase detector on FPGA / Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm and Manfred Glesner -- Case study : implementation of a virtual instrument on a dynamically reconfigurable platform / Gerd Van den Branden, Geert Braeckman, Abdellah Touhafi and Erik Dirkx -- Configurable embedded core for controlling electro-mechanical systems / Rodrigo Piedade and Leonel Sousa -- Evaluation of a locomotion algorithm for worm-like robots on FPGA-embedded processors / J. Gonzalez-Gomez, I. Gonzalez, F. Gomez-Arribas and E. Boemo -- Dynamic partial reconfigurable FIR filter design / Yeong-Jae Oh, Hanho Lee and Chong-Ho Lee -- Event-driven simulation engine for spiking neural networks on a chip / Rodrigo Agis, Javier Diaz, Eduardo Ros, Richard Carrillo and Eva. M. Ortigosa -- Towards an optimal implementation of MLP in FPGA / E. M. Ortigosa, A. Canas, R. Rodriguez, J. Diaz and S. Mota -- Energy consumption for transport of control information on a segmented software-controlled communication architecture / Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen Debosschere and Wilfried Philips -- Quality driven dynamic low power reconfiguration of handhelds / Hiren Joshi, S. S. Verma and G. K. Sharma -- An efficient estimation method of dynamic power dissipation on VLSI interconnects / Joong-ho Park, Bang-Hyun Sung and Seok-Yoon Kim -- Highly paralellized architecture for image motion estimation / Javier Diaz, Eduardo Ros, Sonia Mota and Rafael Rodriguez-Gomez -- Design exploration of a video pre-processor for an FPGA based SoC / Niklas Lepisto, Benny Thornberg and Mattias O'Nils -- QUKU : a fast run time reconfigurable platform for image edge detection / Sunil Shukla, Neil W. Bergmann and Jurgen Becker -- Applications of small-scale reconfigurability to graphics processors / Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys and Kevin Skadron -- An embedded multi-camera system for simultaneous localization and mapping / Vanderlei Bonato, Jose A. de Holanda and Eduardo Marques -- Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor / Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura and Hideharu Amano -- Trigonometric computing embedded in a dynamically reconfigurable CORDIC system-on-chip / Francisco Fons, Mariano Fons, Enrique Canto and Mariano Lopez -- Handel-C design enhancement for FPGA-based DV decoder / Slawomir Cichon, Marek Gorgon and Miroslaw Pac -- Run-time resources management on coarse grained, packet-switching reconfigurable architecture : a case study through the APACHES' platform / Alex Ngouanga, Giles Sassatelli, Lionel Torres, Thierry Gil, Andre Borin Suarez and Altamiro Amadeu Susin -- A new VLSI architecture of lifting-based DWT / Young-Ho Seo and Dong-Wook Kim -- Architecture based on FPGA's for real-time image processing / Ignacio Bravo, Pedro Jimenez, Manuel Mazo, Jose Luis Lazaro and Ernesto Martin -- Real time image processing on a portable aid device for low vision patients / E. Ros, J. Diaz, S. Mota, F. Vargas-Martin and M. D. Pelaez-Coca -- General purpose real-time image segmentation system / S. Mota, E. Ros, J. Diaz and F. de Toro -- Implementation of LPM address generators on FPGAs / Hui Qin, Tsutomu Sasao and Jon T. Butler -- Self reconfiguring EPIC soft core processors / Rainer Scholz and Klaus Buchenrieder -- Constant complexity management of 2D HW multitasking in run-time reconfigurable FPGAs / S. Roman, J. Septien, H. Mecha and D. Mozos -- Area/performance improvement of NoC architectures / Mario P. Vestias and Horacio C. Neto -- Implementation of inner product architecture for increased flexibility in bitwidths of input array / Kwangsup So, Jinsang Kim, Won-Kyung Cho, Young-Soo Kim and Doug Young Suh -- A flexible multi-port caching scheme for reconfigurable platforms / Su-Shin Ang, George Constantinides, Peter Cheung and Wayne Luk -- Enhancing a reconfigurable instruction set processor with partial predication and virtual opcode support / Nikolaos Vassiliadis, George Theodoridis and Spiridon Nikolaidis -- A reconfigurable data cache for adaptive processors / D. Benitez, J. C. Moure, D. I. Rexachs and E. Luque -- The emergence of non-von Neumann processors / Daniel S. Poznanovic -- Scheduling reconfiguration activities of run-time reconfigurable RTOS using an aperiodic task server / Marcelo Gotz and Florian Dittmann -- A new approach to assess defragmentation strategies in dynamically reconfigurable FPGAs / Manuel G. Gericota, Gustavo R. Alves, Luis F. Lemos and Jose M. Ferreira -- A 1,632 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI / Minoru Watanabe and Fuminori Kobayashi -- PISC : polymorphic instruction set computers / Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu-Panainte, Georgi Gaydadjiev, Koen Bertels and Dmitry Cheresiz -- Generic network interfaces for plug and play NoC based architecture / Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia and Poras Balsara -- Providing QoS guarantees in a NoC by virtual channel reservation / Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte and Pierre G. Jasen -- Efficient floating-point implementation of high-order (N)LMS adaptive filters in FPGA / Milan Tichy, Jan Schier and David Gregg -- A reconfigurable architecture for MIMO square root decoder / Hongzhi Wang, Pierre Leray and Jacques Palicot -- Time-memory trade-off attack on FPGA platforms : UNIX password cracking / Nele Mentens, Lejla Batina, Bart Preneel and Ingrid Verbauwhede -- Updates on the security of FPGAs against power analysis attacks / F.-X. Standaert, F. Mace, E. Peeters and J.-J. Quisquater -- Reconfigurable modular arithmetic logic unit for high-performance public-key cryptosystems / K. Sakiyama, N. Mentens, L. Batina, B. Preneel and I. Verbauwhede -- FPGA implementation of a GF(2[superscript m]) Tate pairing architecture / Maurice Keller, Tim Kerins, Francis Crowe and William Marnane -- Iterative modular division over GF(2[superscript m]) : novel algorithm and implementations on FPGA / Guerric Meurice de Dormale and Jean-Jacques Quisquater -- Mobile fingerprint identification using a hardware accelerated biometric service provider / David Rodriguez, Juan M. Sanchez and Arturo Duran -- UNITE : uniform hardware-based network intrusion detection engine / S. Yusuf, W. Luk, M. K. N. Szeto and W. Osborne -- Impact of loop unrolling on area, throughput and clock frequency in ROCCC : C to VHDL compiler for FPGAs / Betul Buyukkurt, Zhi Guo and Walid A. Najjar -- Automatic compilation framework for Bloom filter based intrusion detection / Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt and Walid A. Najjar -- A basic data routing model for a coarse-grain reconfigurable hardware / Jie Guo, Gleb Belov and Gerhard P. Fettweis -- Hardware and a tool chain for ADRES / Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aissa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim and Suk Jin Kim -- Integrating custom instruction specifications into C development processes / Jack Whitham and Neil Audsley -- A compiler-oriented architecture description for reconfigurable systems / Jens Braunes and Rainer G. Spallek -- Dynamic instruction merging and a reconfigurable array : dataflow execution with software compatibility / Antonio Carlos S. Beck, Victor F. Gomes and Luigi Carro -- High-level synthesis using SPARK and systolic array / Jae-Jin Lee and Gi-Yong Song -- Super semi-systolic array-based application-specific PLD architecture / Jae-Jin Lee and Gi-Yong Song.
530 $aAlso issued online.
650 0 $aAdaptive computing systems$vCongresses.
650 0 $aField programmable gate arrays$vCongresses.
700 1 $aBertels, Koen.
700 1 $aCardoso, Joao M. P.
700 1 $aVassiliadis, Stamatis.
938 $aOtto Harrassowitz$bHARR$nhar065015070$c64.20 EUR
938 $aBaker & Taylor$bBKTY$c84.00$d84.00$i354036708X$n0006930248$sactive
938 $aYBP Library Services$bYANK$n2469321
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949 $aQA 76.9.A3 A73 2006$i31786102309967
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999 $aQA 76.9 .A3 A73 2006$wLC$c1$i31786102309967$d8/3/2007$e7/12/2007 $lCIRCSTACKS$mNULS$n1$rY$sY$tBOOK$u11/7/2006