| Record ID | marc_records_scriblio_net/part26.dat:169076619:920 |
| Source | Scriblio |
| Download Link | /show-records/marc_records_scriblio_net/part26.dat:169076619:920?format=raw |
LEADER: 00920cam 2200229 a 4500
001 97105422
003 DLC
005 19970724120451.9
008 970116s1997 maua b 001 0 eng
010 $a 97105422
020 $a0792398270 (acid-free paper)
040 $aDLC$cDLC$dDLC
050 00 $aTK7874.75$b.B45 1997
245 00 $aBehavioral synthesis and component reuse with VHDL /$cAhmed A. Jerraya ... [et al.] ; contribution by E. Berrebi, W. Cesario, P. Guillaume.
260 $aBoston :$bKluwer Academic Publishers,$cc1997.
300 $axix, 263 p. :$bill. ;$c24 cm.
504 $aIncludes bibliographical references (p. 247-255) and index.
650 0 $aIntegrated circuits$xVery large scale integration$xDesign$xData processing.
650 0 $aVHDL (Computer hardware description language)
650 0 $aComputer-aided design.
650 0 $aSystem design$xData processing.
700 1 $aJerraya, Ahmed A.$q(Ahmed Amine)