| Record ID | marc_records_scriblio_net/part27.dat:75727023:929 |
| Source | Scriblio |
| Download Link | /show-records/marc_records_scriblio_net/part27.dat:75727023:929?format=raw |
LEADER: 00929cam 2200253 a 4500
001 98023993
003 DLC
005 20000829163004.0
008 980422s1998 mau b 001 0 eng
010 $a 98023993
020 $a079238184X (alk. paper)
040 $aDLC$cDLC$dDLC$dDLC
050 00 $aTK7874$b.H82 1998
082 00 $a621.3815$221
100 1 $aHuang, Shi-Yu,$d1965-
245 10 $aFormal equivalence checking and design debugging /$cby Shi-Yu Huang and Kwang-Ting (Tim) Cheng.
260 $aBoston :$bKluwer Academic Publishers,$cc1998.
300 $axviii, 229 p. ;$c24 cm.
440 0 $aFrontiers in electronic testing
504 $aIncludes bibliographical references (p. [211-222) and index.
650 0 $aIntegrated circuits$xVerification.
650 0 $aElectronic circuit design$xData processing.
650 0 $aApplication specific integrated circuits$xDesign and construction.
700 1 $aCheng, Kwang-Ting,$d1961-