An edition of A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits
(1987)
A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits
by Daniel L. Palumbo
Share
×Close
This edition doesn't have a description yet. Can you add one?
Publish Date
1987
Publisher
National Aeronautics and Space Administration, Scientific and Technical Information Office,
For sale by the National Technical Information Service]
Language
English
Buy this book
Subjects
Electronic digital computers, Evaluation| Edition | Availability |
|---|---|
1
A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits
1987, National Aeronautics and Space Administration, Scientific and Technical Information Office, For sale by the National Technical Information Service]
Microform
in English
|
aaaa
|
Book Details
Edition Notes
Distributed to depository libraries in microfiche.
Microfiche. [Washington, D.C.? : National Aeronautics and Space Administration], 1987. 1 microfiche.
The Physical Object
ID Numbers
Community Reviews (0)
Feedback?
| January 19, 2010 | Edited by WorkBot | add subjects and covers |
| December 11, 2009 | Created by WorkBot | add works page |