An edition of Design of cost-efficient interconnect processing units (2009)

Design cost-efficient interconnect processing units

the Spidergon STNoC

Cover of: Design cost-efficient interconnect processing units by authors, Miltos D. Grammatikakis ... [et al.].
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Last edited by ImportBot
July 29, 2014 | History
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An edition of Design of cost-efficient interconnect processing units (2009)

Design cost-efficient interconnect processing units

the Spidergon STNoC

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Publish Date
Publisher
Taylor & Francis
Language
English

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Previews available in: English

Subjects

ST Microelectronics, Networks on a chip, Microprocessors
Edition Availability
Cover of: Design cost-efficient interconnect processing units
Design cost-efficient interconnect processing units: the Spidergon STNoC
2009, Taylor & Francis
in English

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Book Details

Edition Notes

"A CRC title."

Includes bibliographical references and index.

Published in
Boca Raton
Series
System-on-chip design and technologies -- 2

Classifications

Dewey Decimal Class
004.1
Library of Congress
TK5105.546 .D47 2009

The Physical Object

Pagination
p. cm.

Edition Identifiers

Open Library
OL19889840M
Internet Archive
designcosteffici00copp
ISBN 13
9781420044713
LCCN
2008026558
Library Thing
7233086
Goodreads
2427946

Work Identifiers

Work ID
OL16972296W

Source records

Internet Archive item record

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History

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