An edition of System-on-chip test architectures
(2007)
System-On-Chip Test Architectures
Nanometer Design for Testability
by Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba
Share
×Close
This edition doesn't have a description yet. Can you add one?
Check nearby libraries
Buy this book
Previews available in: English
Subjects
Very large scale integration, Testing, Design, Integrated circuits, Systems on a chip, Electrical engineering, Technology & Engineering, Computers - General Information, Science/Mathematics, Electricity, Logic Design, Computers & Internet, Technology / Engineering / Electrical, Engineering - Electrical & Electronic, Design, Integrated circuits, Systems on a chip, Testing, Very large scale integration, Integrated circuits, very large scale integration| Edition | Availability |
|---|---|
1
System-On-Chip Test Architectures: Nanometer Design for Testability
2010, Elsevier Science & Technology Books
in English
0080556809 9780080556802
|
aaaa
|
2
System-on-chip test architectures: nanometer design for testability
2008, Morgan Kaufmann Publishers
in English
012373973X 9780123739735
|
zzzz
|
3
System-on-Chip Test Architectures (Systems on Silicon)
November 16, 2007, Morgan Kaufmann
Hardcover
in English
012373973X 9780123739735
|
zzzz
|
Book Details
Classifications
The Physical Object
Edition Identifiers
Work Identifiers
Community Reviews (0)
History
- Created December 25, 2021
- 1 revision
Wikipedia citation
×CloseCopy and paste this code into your Wikipedia page. Need help?
| December 25, 2021 | Created by ImportBot | Imported from Better World Books record |