An edition of Design of CMOS RF integrated circuits and systems
(2010)
Design of CMOS RF integrated circuits and systems
by Kiat Seng Yeo
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"This book provides the most comprehensive and in-depth coverage of the latest circuit design developments in RF CMOS technology. It is a practical and cutting-edge guide, packed with proven circuit techniques and innovative design methodologies for solving challenging problems associated with RF integrated circuits and systems. This invaluable resource features a collection of the finest design practices that may soon drive the system-on-chip revolution. Using this book's state-of-the-art design techniques, one can apply existing technologies in novel ways and to create new circuit designs for the future."--BOOK JACKET.
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| Edition | Availability |
|---|---|
1
Design of CMOS RF integrated circuits and systems
2010, World Scientific
in English
9814271551 9789814271554
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Book Details
Table of Contents
Chapter 1. RF CMOS Systems on Chips
1.1. Modern RF Mobile Technologies
1.2. The RF Transceiver System
1.3. Modulation and Demodulation Techniques
1.4. Multiple Access Techniques
1.5. Receiver Sensitivity and Linearity
1.6. On-chip Power Amplifier
1.7. The Cellular Phone Concept
1.8. The CMOS RF Technology
References
Chapter 2. RF CMOS Devices and Process Design Kits
2.1. Introduction
2.2. RF Transistors
2.2.1. BSIM3v3 Model
2.2.2. BSIM4 Model
2.2.3. Figure of Merit
2.2.3.1. fT definition and extraction
2.2.3.2. fMAX definition and extraction
2.2.4. RF Parasitics in MOSFETs
2.2.5. Scalable RF CMOS Transistor Modeling
2.2.5.1. RF MOSFET model
2.2.5.2. Gate resistance modeling
2.2.5.3. Source and drain resistance modeling
2.2.5.4. Gate to substrate capacitance and resistance modeling
2.2.5.5. Gate to source and gate to drain capacitance modeling
2.2.5.6. Drain to source capacitance modeling
2.2.5.7. Substrate resistance modeling
2.3. On-chip Inductors
2.3.1. Spiral Inductors on Silicon
2.3.1.1. Figure of merits
2.3.2. Advantages of Silicon-based Spiral Inductors
2.3.3. Identifying Loss Mechanisms in Silicon-based Spiral Inductors
2.3.3.1. Metallization resistive loss
2.3.3.2. Substrate capacitive and resistive loss
2.3.3.3. Substrate eddy current
2.3.4. Q-Factor Enhancement Techniques
2.3.4.1. Q-factor enhancement using processing technologies
2.3.4.2. Q-factor enhancement using active inductors
2.3.4.3. Q-factor enhancement using coupled spiral coils
2.3.4.4. Q-factor enhancement using layout optimization
2.3.4.5. Q-factor enhancement using inductor device model
2.3.4.6. Figure of merits for differential spiral inductors
2.4. Baluns/Transformers
2.4.1. The Ideal Transformer
2.4.2. Transformer Types
2.4.3. Inductance, Capacitance, and Resistance
2.4.4. Coupling Coefficient k, Turn Ratio n, and Quality Factor Q
2.4.5. Patterned Ground Shield
2.4.6. Designing the Transformer
2.5. RF Interconnects
2.5.1. Transmission Line Concept
2.5.1.1. Transmission line constants
2.5.1.2. Transmission line impedances
2.5.1.3. Reflection and voltage standing wave ratio
2.5.1.4. Frequency-dependent charge distribution
2.5.1.5. Effects of dielectric on interconnects
2.5.2. Existing Methodologies to Tackle Post Layout Parasitics
2.5.3. Proposed Figure of Merit for RF Interconnects
2.6. Varactors
2.6.1. Functions of Varactors
2.6.2. Varactor Design
2.7. RF Capacitors
2.7.1. Capacitance
2.7.2. Geometry
2.7.3. Quality Factor and Series Resistance
2.7.4. Capacitance Modeling
2.7.5. Impedances
2.7.6. Design Considerations
2.8. Process Design Kits
2.8.1. Benefits
2.8.2. Advanced Device Modeling and Front-end Design
2.8.3. Back-end Design and Accelerated Layout
2.8.4. Physical Verification and Silicon Analysis
2.8.5. Future of Process Design Kits
2.9. Summary
References
Chapter 3. RF CMOS Low Noise Amplifiers
3.1. Basic Concepts of LNAs
3.1.1. Operating Frequency
3.1.2. Sensitivity
3.1.3. Noise Figure and Voltage Gain
3.1.4. 1 -dB Compression Point
3.1.5. The 3rd Order Intercept Point
3.1.6. S-Parameters
3.2. Input Architecture of LNAs
3.2.1. Common Source Stage with Resistive Termination
3.2.2. Common Gate Stage
3.2.3. Common Source Stage with Shunt Feedback
3.2.4. Common Source Stage with Source Inductive Degeneration
3.3. Input Matching Analysis
3.4. Design of a Single-band LNA (LNA1)
3.4.1. Noise Figure Optimization
3.4.2. Design Methodology
3.4.3. Measurement Results
3.5. Summary
References
Chapter 4. RF Mixers
4.1. Introduction
4.2. Common Configurations of Active Mixers
4.3. Active Mixer with Current Booster
4.4. Passive Mixers
4.5. Port Isolation and DC Offset in Direct Conversion Mixers
4.6. Image Reject Mixers for Low IF Architectures
References
Chapter 5. RF CMOS Oscillators
5.1. Introduction
5.1.1. Ring Oscillator
5.1.2. LC Oscillator
5.2. Various LC VCO Topologies
5.2.1. Colpitts and HartleyLC VCOs
5.2.2. Differential LC VCOs
5.2.2.1. Complementary LC VCOs
5.2.2.2. Tail current source of LC VCOs
5.3. LC VCO Design Methodology
5.3.1. Topology
5.3.1.1. Operation theory
5.3.1.2. Equivalent circuit of cross-coupled LC tank VCO
5.3.2. Associated Noise Sources of Complementary LC Tank VCO
5.3.2.1. Noise sources of the LC tank
5.3.2.2. Upconversion of 1/f noise in the tail transistor
5.3.3. Noise Sources in Active Devices
5.3.3.1. High frequency noise
5.3.3.2. Noise sources in cross-coupled transistors
5.3.3.3. Optimization of channel length Lch
5.3.4. Linear Time Variant (LTV) Phase Noise Analysis
5.3.4.1. Definition of Impulse Sensitivity Function (ISF)-Γ(ω0t)
5.3.4.2. Parameterized phase impulse response hφ (t, τ) using ISF
5.3.4.3. Phase noise calculation
5.3.4.4. Steps to achieve minimal phase noise
5.3.5. A 2GHz Cross-Coupled LC Tank VCO
5.3.5.1. 2GHz cross-coupled LC tank VCO
5.3.5.2. Verifications and discussions
5.3.5.3. Experimental results
5.3.6. A 9.3 ̃10.4GHz Cross-Coupled Complementary Oscillator
5.3.6.1. Phase noise estimation for 10GHzLC tank VCO
5.3.6.2. Experimental results
5.4. Summary
References
Chapter 6. RF CMOS Phase-Locked Loops
6.1. Fundamental Principles of a Phase-Locked Loop (PLL)
6.2. Transient Characteristics - Tracking
6.3. Loop Bandwidth - Second Order PLL
6.4. Acquisition
6.5. Phase Detector and Loop Filter
6.5.1. Phase Detector
6.5.1.1. Multiplier
6.5.1.2. EXOR gate
6.5.1.3. Flip-flop phase detector
6.5.1.4. Phase frequency detector
6.5.2. Loop Filter
6.6. Charge Pump PLL Filter
6.7. Noise Characteristics of PLL Building Blocks
6.7.1. Phase Noise of VCO
6.7.2. Phase Noise of Reference Input Signal
6.7.3. Phase Noise of Frequency Divider
6.7.4. Phase Noise of Loop Filter
6.7.5. Optimum Loop Bandwidth
6.8. Summary
References
Chapter 7. RF CMOS Prescalers
7.1. Prescaler
7.1.1. Dual-Modulus Prescaler
7.1.2. Dual-Modulus Prescaler with Pulse Swallow Counter
7.1.3. Integer-N Architecture through Dual-Modulus Prescaler with Pulse Swallow Counter
7.2. DFFs for Prescaler
7.2.1. MCML
7.2.2. CMOS Dynamic Circuit
7.3. Design and Optimization of CMOS Dynamic Circuit (CDC) Based Prescaler
7.3.1. E-TSPC Based Divide-by-2 Unit
7.3.2. E-TSPC Based Divide-by-2/3 Unit
7.3.3. Design Example
7.3.4. Simulation and Silicon Verifications
7.4. Summary
References.
Edition Notes
Includes bibliographical references and index.
Classifications
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History
- Created February 8, 2012
- 6 revisions
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